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| Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5607B Rev. 3, 01/2010 MPC5607B Microcontroller Data Sheet Features * Single issue, 32-bit CPU core complex (e200z0h) -- Compliant with the Power ArchitectureTM embedded category -- Enhanced instruction set allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. Up to 1.5 Mbytes on-chip Flash supported with the Flash controller Up to 96 Kbytes on-chip SRAM Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity on certain family members Interrupt controller (INTC) capable of handling 204 selectable-priority interrupt sources Frequency modulated phase-locked loop (FMPLL) Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters 16-channel eDMA controller with multiple transfer request sources using DMA multiplexer Boot assist module (BAM) supports internal Flash programming via a serial link (CAN or SCI) Timer supports I/O channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS) 2 analog-to-digital converters (ADC): one 10-bit and one 12-bit Cross Trigger Unit to enable synchronization of ADC conversions with a timer event from the eMIOS or PIT 176LQFP (24 x 24) 144 LQFP (20 x 20 ) 208 MAPBGA (17 x 17 ) 100 LQFP (14 x 14 ) * * * * * * * * * * * * * * * * * * * Up to 6 serial peripheral interface (DSPI) modules Up to 10 serial communication interface (LINFlex) modules Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers 1 inter-integrated circuit (I2C) interface module Up to 149 configurable general purpose pins supporting input and output operations (package dependent) Real-Time Counter (RTC) -- Clock source from internal 128 kHz or 16 MHz oscillator supporting autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds -- Optional support for RTC with clock source from external 32 kHz crystal oscillator, supporting wakeup with 1 sec resolution and maximum timeout of 1 hour Up to 8 periodic interrupt timers (PIT) with 32-bit counter resolution Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus Device/board boundary scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) On-chip voltage regulator (VREG) for regulation of input supply for all internal levels * * This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2010. All rights reserved. Preliminary--Subject to Change Without Notice Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages MPC5607B Table of Contents 2 3 4 5 6 MPC5607B Microcontroller Data Sheet, Rev. 3 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 1 General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1 176LQFP pin configuration . . . . . . . . . . . . . . . . . . . . . . .8 2.2 144LQFP pin configuration . . . . . . . . . . . . . . . . . . . . . . .9 2.3 208MAPBGA pin configuration . . . . . . . . . . . . . . . . . . .10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2.1 NVUSRO[PAD3V5V] field description . . . . . . . .11 3.2.2 NVUSRO[OSCILLATOR_MARGIN] field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.2.3 NVUSRO[WATCHDOG_EN] field description . .12 3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .13 3.4 Recommended operating conditions . . . . . . . . . . . . . .14 3.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .17 3.5.1 External ballast resistor recommendations . . . .17 3.5.2 Package thermal characteristics . . . . . . . . . . . .17 3.5.3 Power considerations. . . . . . . . . . . . . . . . . . . . .18 3.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .18 3.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . .19 3.6.3 I/O output DC characteristics. . . . . . . . . . . . . . .21 3.6.4 Output pin transition times . . . . . . . . . . . . . . . . .23 3.6.5 I/O pad current specification . . . . . . . . . . . . . . .24 3.7 nRSTIN electrical characteristics . . . . . . . . . . . . . . . . .27 3.8 Power management electrical characteristics. . . . . . . .30 3.8.1 Voltage regulator electrical characteristics . . . .30 3.8.2 Voltage monitor electrical characteristics. . . . . .33 3.9 Low voltage domain power consumption . . . . . . . . . . .35 3.10 Flash memory electrical characteristics . . . . . . . . . . . .37 3.10.1 Program/Erase characteristics. . . . . . . . . . . . . .37 3.10.2 Flash power supply DC characteristics . . . . . . .38 3.10.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 40 3.11 Electromagnetic compatibility (EMC) characteristics. . 40 3.11.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.11.2 Electromagnetic interference (EMI) . . . . . . . . . 41 3.11.3 Absolute maximum ratings (electrical sensitivity)41 3.12 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.13 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 48 3.15 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 50 3.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.17.2 Input impedance and ADC accuracy . . . . . . . . 51 3.17.3 ADC electrical characteristics . . . . . . . . . . . . . 56 3.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 64 3.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 66 3.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 73 3.18.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 74 Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 75 4.1.1 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.1.2 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.3 100 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.1.4 208MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 General description 1 General description Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages The MPC5607B is a new family of next generation microcontrollers built on the Power ArchitectureTM embedded category. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. The MPC5607B family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of the MPC5607B automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU (Auxillary Processor Unit), providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. Table 1. MPC5607B Family Comparison1 Feature Package CPU Execution speed Code Flash Data Flash RAM MPU DMA 10-bit ADC dedicated 4 3 MPC5605B 100 LQFP 144 LQFP 176 LQFP MPC5606B 144 LQFP e200z0h Up to 64 MHz 176 LQFP MPC5607B 176 LQFP 208 MAP BGA2 768 KB 1 MB 64 (4 x 16) Kbyte 1.5 MB 64 KB 80 KB 8-entry 16 ch Yes 96 KB 7 ch 15 ch 29 ch 15 ch 19 ch Yes 29 ch shared with 12-bit ADC 12-bit ADC dedicated 5 5 ch 19 ch 37 ch, 16-bit 10 ch 7 ch 7 ch 13 ch 4 3 6 5 8 6 6 5 6 14 ch 33 ch 8 6 10 64 ch, 16-bit shared with 10-bit ADC Total timer I/O eMIOS 6 Counter / OPWM / ICOC7 O(I)PWM / OPWFMB / OPWMCB / ICOC8 O(I)PWM / ICOC9 OPWM / ICOC SCI (LINFlex) SPI (DSPI) CAN (FlexCAN) 10 MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3 General description Table 1. MPC5607B Family Comparison1 (continued) Feature I2C 32 kHz oscillator GPIO11 Debug 1 2 MPC5605B MPC5606B 1 Yes MPC5607B Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 77 121 149 JTAG 121 149 149 N2+ Feature set dependent on selected peripheral multiplexing; table shows example. 208 MAPBGA package is for debug use only. 3 Based on 105 C ambient operating temperature. 4 Not shared with 12-bit ADC, but possibly shared with other alternate functions. 5 Not shared with 10-bit ADC, but possibly shared with other alternate functions. 6 Refer to eMIOS section of device reference manual for information on the channel configuration and functions. 7 Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output Compare. 8 Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output Compare. 9 Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and Pulse width measurement. 10 Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare. 11 Maximum I/O count based on multiplexing with peripherals. 1.1 Block diagram Figure 1 shows a top-level block diagram of the MPC5607B. MPC5607B Microcontroller Data Sheet, Rev. 3 4 Preliminary--Subject to Change Without Notice Freescale Semiconductor General description JTAG JTAG Port Nexus Port Nexus NMI SIUL Voltage Regulator NMI Interrupt requests from peripheral blocks INTC Clocks FMPLL CMU eDMA (Master) Instructions e200z0h (Master) Data Nexus 2+ (Master) RAM 96 KB Code Flash DataFlash 1.5 MB 64 KB SRAM Controller MPU Flash Controller (Slave) (Slave) (Slave) MPU Registers WKPU RTC STM SWT ECSM PIT MC_RGM MC_CGM MC_ME MC_PCU BAM SSCM Peripheral Bridge Interrupt Request SIUL Reset Control External Interrupt Request IMUX GPIO & Pad Control 19 ch 10bit/12bit 29 ch 10-bit ADC ADC CTU 64 ch eMIOS 10 x LINFlex 6x DSPI I2C 6x FlexCAN I/O Legend: ADC BAM CAN CMU CTU DSPI eMIOS FMPLL I2C IMUX INTC JTAG LINFlex MC_CGM ... ... ... ... ... Analog-to-Digital Converter Boot Assist Module Controller Area Network (FlexCAN) Clock Monitor Unit Cross Triggering Unit Deserial Serial Peripheral Interface Enhanced Modular Input Output System Frequency-Modulated Phase-Locked Loop Inter-integrated Circuit Bus Internal Multiplexer Interrupt Controller JTAG controller Serial Communication Interface (LIN support) Clock Generation Module MC_ME MPU Nexus NMI MC_PCU MC_RGM PIT RTC SIUL SRAM SSCM STM SWT Mode Entry Module Memory Protection Unit NexuS Development Interface (NDI) Level Non-Maskable Interrupt Power Control Unit Reset Generation Module Periodic Interrupt Timer Real-Time Clock System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Figure 1. MPC5607B block diagram MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 64-bit 2 x 3 Crossbar Switch General description Table 2 summarizes the functions of the blocks present on the MPC5607B. Table 2. MPC5607B series block summary Block Function Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Analog-to-digital converter (ADC) Converts analog voltages to digital values Boot assist module (BAM) Clock generation module (MC_CGM) Crossbar switch (XBAR) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Provides logic and control required for the generation of system and peripheral clocks Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Cross triggering unit (CTU) Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices (DSPI) Enhanced modular input output system (eMIOS) Flash memory Provides the functionality to generate or measure events Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol Frequency-modulated phase-locked loop (FMPLL) Internal multiplexer (IMUX) SIU subblock Generates high-speed system clocks and supports programmable frequency modulation Allows flexible mapping of peripheral interface on the different pins of the device Inter-integrated circuit (I2CTM) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Interrupt controller (INTC) JTAG controller LINFlex controller Memory protection unit (MPU) Periodic interrupt timer (PIT) Real-time counter (RTC) Provides priority-based preemptive scheduling of interrupt requests Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Provides hardware access control for all memory references generated in a device Produces periodic interrupts and triggers A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) MPC5607B Microcontroller Data Sheet, Rev. 3 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Package pinouts Table 2. MPC5607B series block summary (continued) Block Reset generation module (MC_RGM) Static random-access memory (SRAM) Function Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Centralizes reset sources and manages the device reset sequence of the device Provides storage for program code, constants, and variables System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration System timer module (STM) Provides a set of output compare events to support AutoSAR and operating system tasks 2 Package pinouts The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions, please refer to the device reference manual. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7 Package pinouts 2.1 176LQFP pin configuration PB[2]/GPIO[18]/LIN0TX/SDA/E0UC[30] PC[8]/GPIO[40]/LIN2TX/E0UC[3] PC[13]/GPIO[45]/E0UC[13]/SOUT_2 PC[12]/GPIO[44]/E0UC[12]/EIRQ[19]/SIN_2 PI[0]/GPIO[128]/E0UC[28]/LIN8TX PI[1]/GPIO[129]/E0UC[29]/WKUP[24]/LIN8RX PI[2]/GPIO[130]/E0UC[30]/LIN9TX PI[3]/GPIO[131]/E0UC[31]/WKUP[23]/LIN9RX PE[7]/GPIO[71]/E0UC[23]/CS2_0/MA[0]/EIRQ[23] PE[6]/GPIO[70]/E0UC[22]/CS3_0/MA[1]/EIRQ[22] PH[8]/GPIO[120]/E1UC[10]/CS2_2/MA[0] PH[7]/GPIO[119]/E1UC[9]/CS3_2/MA[1] PH[6]/GPIO[118]/E1UC[8]/MA[2] PH[5]/GPIO[117]/E1UC[7] PH[4]/GPIO[116]/E1UC[6] PE[5]/GPIO[69]/E0UC[21]/CS0_1/MA[2] PE[4]/GPIO[68]/E0UC[20]/SCK_1/EIRQ[9] PC[4]/GPIO[36]/E1UC[31]/EIRQ[18]/SIN_1/CAN3RX PC[5]/GPIO[37]/SOUT_1/CAN3TX/EIRQ[7] PE[3]/GPIO[67]/E0UC[19]/SOUT_1 PE[2]/GPIO[66]/E0UC[18]/EIRQ[21]/SIN_1 PH[9]/GPIO[121]/TCK PC[0]/GPIO[32]/TDI VSS_LV VDD_LV VDD_HV VSS_HV PC[1]/GPIO[33]/TDO PH[10]/GPIO[122]/TMS PA[6]/GPIO[6]/E0UC[6]/CS1_1/EIRQ[1]/LIN4RX PA[5]/GPIO[5]/E0UC[5]/LIN4TX PC[2]/GPIO[34]/SCK_1/CAN4TX/EIRQ[5] PC[3]/GPIO[35]/CS0_1/MA[0]/EIRQ[6]/CAN4RX/CAN1RX PI[4]/GPIO[132]/E1UC[28]/SOUT_4 PI[5]/GPIO[133]/E1UC[29]/SCK_4 PH[12]/GPIO[124]/SCK_3/CS1_4/E1UC[25] PH[11]/GPIO[123]/SOUT_3/CS0_4/E1UC[5] PG[11]/GPIO[107]/E0UC[25]/CS0_4 PG[10]/GPIO[106]/E0UC[24]/E1UC[31]/SIN_4 PE[15]/GPIO[79]/CS0_2/E1UC[22] PE[14]/GPIO[78]/SCK_2/E1UC[21]/EIRQ[12] PG[15]/GPIO[111]/E1UC[1]/LIN8RX PG[14]/GPIO[110]/E1UC[0]/LIN8TX PE[12]/GPIO[76]/E1UC[19]/EIRQ[11]/SIN_2/ADC1_S[7] LIN0RX/WKUP[11]/SCL/E0UC[31]/GPIO[19]/PB[3] LIN2RX/WKUP[13]/E0UC[7]/GPIO[41]/PC[9] EIRQ[8]/SCK2/E0UC[14]/GPIO[46]/PC[14] EIRQ[20]/CS0_2/E0UC[15]/GPIO[47]/PC[15] E1UC[18]/SCK_5/GPIO[148]/PJ[4] VDD_HV VSS_HV E1UC[17]/SOUT_5/GPIO[127]/PH[15] E1UC[26]/CS0_3/SOUT_4/GPIO[125]/PH[13] E1UC[27]/CS1_3/SCK_4/GPIO[126]/PH[14] CS0_4/E1UC[30]/GPIO[134]/PI[6] CS1_4/E1UC[31]/GPIO[135]/PI[7] SIN_3/WKUP[18]/E1UC[14]/GPIO[101]/PG[5] SCK_3/E1UC[13]/GPIO[100]/PG[4] WKUP[17]/CS0_3/E1UC[12]/GPIO[99]/PG[3] SOUT_3/E1UC[11]/GPIO[98]/PG[2] MA[2]/WKUP[3]/E0UC[2]/GPIO[2]/PA[2] CAN5RX/WKUP[6]/E0UC[16]/GPIO[64]/PE[0] WKUP[2]/NMI/E0UC[1]/GPIO[1]/PA[1] CAN5TX/E0UC[17]/GPIO[65]/PE[1] CAN3TX/E0UC[22]/CAN2TX/GPIO[72]/PE[8] CAN3RX/CAN2RX/WKUP[7]/E0UC[23]/GPIO[73]/PE[9] EIRQ[10]/E1UC[30]/CS3_1/LIN3TX/GPIO[74]/PE[10] WKUP[19]/E0UC[13]/CLKOUT/E0UC[0]/GPIO[0]/PA[0] LIN3RX/WKUP[14]/CS4_1/E0UC[24]/GPIO[75]/PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV LIN7RX/WKUP[21]/SCK_2/E1UC[18]/GPIO[105]/PG[9] EIRQ[15]/CS0_2/LIN7TX/E1UC[17]/GPIO[104]/PG[8] CAN4RX/CAN1RX/WKUP[5]/MA[2]/GPIO[43]/PC[11] MA[1]/CAN4TX/CAN1TX/GPIO[42]/PC[10] LIN6RX/WKUP[20]/E1UC[30]/E1UC[16]/GPIO[103]/PG[7] LIN6TX/E1UC[15]/GPIO[102]/PG[6] LIN0TX/E0UC[30]/CAN0TX/GPIO[16]/PB[0] CAN0RX/WKUP[4]/LIN0RX/E0UC[31]/GPIO[17]/PB[1] CAN2RX/CAN3RX/WKUP[22]/CS5_0/E1UC[1]/GPIO[89]/PF[9] CAN2TX/CS4_0/CAN3TX/GPIO[88]/PF[8] LIN5TX/E1UC[25]/GPIO[92]/PF[12] E1UC[28]/LIN1TX/GPIO[38]/PC[6] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 LQFP Top view 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PA[11]/GPIO[11]/E0UC[11]/SCL/EIRQ[16]/LIN2RX/ADC1_S[3] PA[10]/GPIO[10]/E0UC[10]/SDA/LIN2TX/ADC1_S[2] PA[9]/GPIO[9]/E0UC[9]/CS2_1/FAB PA[8]/GPIO[8]/E0UC[8]/E0UC[14]/EIRQ[3]/ABS[0]/LIN3RX PA[7]/GPIO[7]/E0UC[7]/LIN3TX/EIRQ[2]/ADC1_S[1] PE[13]/GPIO[77]/SOUT_2/E1UC[20] PF[14]/GPIO[94]/CAN4TX/E1UC[27]/CAN1TX PF[15]/GPIO[95]/E1UC[4]/EIRQ[13]/CAN4RX/CAN1RX VDD_HV VSS_HV PG[0]/GPIO[96]/CAN5TX/E1UC[23] PG[1]/GPIO[97]/E1UC[24]/EIRQ[14]/CAN5RX PH[3]/GPIO[115]/E1UC[5]/CS0_1 PH[2]/GPIO[114]/E1UC[4]/SCK_1 PH[1]/GPIO[113]/E1UC[3]/SOUT_1 PH[0]/GPIO[112]/E1UC[2]/SIN_1 PG[12]/GPIO[108]/E0UC[26]/SOUT_4 PG[13]/GPIO[109]/E0UC[27]/SCK_4 PA[3]/GPIO[3]/E0UC[3]/LIN5TX/CS4_1/EIRQ[0]/ADC1_S[0] PI[13]/GPIO[141]/CS1_3/ADC0_S[21] PI[12]/GPIO[140]/CS0_3/ADC0_S20] PI[11]/GPIO[139]/ANS[19]/SIN_3 PI[10]/GPIO[138]/ADC0_S[18] PI[9]/GPIO[137]/ADC0_S[17] PI[8]/GPIO[136]/ADC0_S[16] PB[15]/GPIO[31]/E0UC[7]/CS4_0/ADC0_X[3] PD[15]/GPIO[63]/CS2_1/E0UC[27]/ADC0_S[7] PB[14]/GPIO[30]/E0UC[6]/CS3_ 0/ADC0_X[2] PD[14]/GPIO[62]/CS1_1/E0UC[26]/ADC0_S[6] PB[13]/GPIO[29]/E0UC[5]/CS2_0/ADC0_X[1] PD[13]/GPIO[61]/CS0_1/E0UC[25]/ADC0_S[5] PB[12]/GPIO[28]/E0UC[4]/CS1_0/ADC0_X[0] PD[12]/GPIO[60]/CS5_0/E0UC[24]/ADC0_S[4] VDD_HV_ADC1 VSS_HV_ADC1 PB[11]/GPIO[27]/E0UC[3]/CS0_0/ADC0_S[3] PD[11]/GPIO[59]/ADC0_P[15]/ADC1_P[15] PD[10]/GPIO[58]/ADC0_P[14]/ADC1_P[14] PD[9]/GPIO[57]/ADC0_P[13]/ADC1_P[13] PB[7]/GPIO[23]/ADC0_P[3]/ADC1_P[3] PB[6]/GPIO[22]/ADC0_P[2]/ADC1_P[2] PB[5]/GPIO[21]/ADC0_P[1]/ADC1_P[1] VDD_HV_ADC0 VSS_HV_ADC0 Note: Availability of port pin alternate functions depends on product selection. Figure 2. 176 LQFP pin configuration (top view) MPC5607B Microcontroller Data Sheet, Rev. 3 8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages LIN1RX/WKUP[12]/E1UC[29]/GPIO[39]/PC[7] E1UC[2]/LIN4TX/CS1_0/GPIO[90]/PF[10] LIN4RX/WKUP[15]/E1UC[3]/CS2_0/GPIO[91]/PF[11] WKUP[10]/E0UC[1]/SCK_0/CS0_0/GPIO[15]/PA[15] LIN5RX/WKUP[16]/E1UC[26]/GPIO[93]/PF[13] EIRQ[4]/E0UC[0]/CS0_0/SCK_0/GPIO[14]/PA[14] LIN5RX/WKUP[9]/CS0_1/E0UC[4]/GPIO[4]/PA[4] E0UC[29]/SOUT_0/GPIO[13]/PA[13] EIRQ[17]/SIN_0/CS3_1/E0UC[28]/GPIO[12]/PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV ADC1_S[5]/OSC32K_EXTAL/WKUP[26]/ADC0_S[1]/GPIO[25]/PB[9] ADC1_S[4]/OSC32K_XTAL/WKUP[25]/ADC_S[0]/GPIO[24]/PB[8] ADC0_S[6]/WKUP[8]/ANS[2]/GPIO[26]/PB[10] ADC0_S[8]/CS3_1/E0UC[10]/GPIO[80]/PF[0] ADC0_S[9]/CS4_1/E0UC[11]/GPIO[81]/PF[1] ADC0_S[10]/CS0_2/E0UC[12]/GPIO[82]/PF[2] ADC0_S[11]/CS1_2/E0UC[13]/GPIO[83]/PF[3] ADC0_S[12]/CS2_2/E0UC[14]/GPIO[84]/PF[4] ADC0_S[13]/CS3_2/E0UC[22]/GPIO[85]/PF[5] ADC0_S14]/CS1_1/E0UC[23]/GPIO[86]/PF[6] ADC0_S[15]/CS2_1/GPIO[87]/PF[7] ADC0_S[27]/CS1_5/GPIO[147]/PJ[3] ADC0_S[26]/CS0_5/GPIO[146]/PJ[2] SIN_5/ANS[25]/GPIO[145]/PJ[1] ADC0_S[24]/CS1_4/GPIO[144]/PJ[0] ADC0_S[23]/CS0_4/GPIO[143]/PI[15] SIN_4/ANS[22]/GPIO[142]/PI[14] ANP[4]/WKUP[27]/GPIO[48]/PD[0] ADC1_P[5]/ADC0_P[5]/WKUP[28]/GPIO[49]/PD[1] ADC1_P[6]/ADC0_P[6]/GPIO[50]/PD[2] ADC1_P[8]/ADC0_P[7]/GPIO[51]/PD[3] ADC1_P[8]/ADC0_P[8]/GPIO[52]/PD[4] ADC1_P[9]/ADC0_P[9]/GPIO[53]/PD[5] ADC0_P[10]/ADC0_P[10]/GPIO[54]/PD[6] ADC1_P[11]/ADC0_P[11]/GPIO[55]/PD[7] VDD_HV VSS_HV ADC1_P[12]/ADC0_P[12]/GPIO[56]/PD[8] ADC1_P[0]/ADC0_P[0]/GPIO[20]/PB[4] 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 2.2 Freescale Semiconductor LIN0RX/WKUP[11]/SCL/E0UC[31]/GPIO[19]/PB[3] LIN2RX/WKUP[13]/E0UC[7]/GPIO[41]/PC[9] EIRQ[8]/SCK2/E0UC[14]/GPIO[46]/PC[14] EIRQ[20]/CS0_2/E0UC[15]/GPIO[47]/PC[15] SIN_3/WKUP[18]/E1UC[14]/GPIO[101]/PG[5] SCK_3/E1UC[13]/GPIO[100]/PG[4] WKUP[17]/CS0_3/E1UC[12]/GPIO[99]/PG[3] SOUT_3/E1UC[11]/GPIO[98]/PG[2] MA[2]/WKUP[3]/E0UC[2]/GPIO[2]/PA[2] CAN5RX/WKUP[6]/E0UC[16]/GPIO[64]/PE[0] WKUP[2]/NMI[0]/E0UC[1]/GPIO[1]/PA[1] CAN5TX/E0UC[17]/GPIO[65]/PE[1] CAN3TX/E0UC[22]/CAN2TX/GPIO[72]/PE[8] CAN3RX/CAN2RX/WKUP[7]/E0UC[23]/GPIO[73]/PE[9] EIRQ[10]/E1UC[30]/CS3_1/LIN3TX/GPIO[74]/PE[10] WKUP[19]/E0UC[13]/CLKOUT/E0UC[0]/GPIO[0]/PA[0] LIN3RX/WKUP[14]/CS4_1/E0UC[24]/GPIO[75]/PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV LIN7RX/EIRQ[21]/SCK_2/E1UC[18]/GPIO[105]/PG[9] EIRQ[15]/CS0_2/LIN7TX/E1UC[17]/GPIO[104]/PG[8] CAN4RX/CAN1RX/WKUP[5]/MA[2]/GPIO[43]/PC[11] MA[1]/CAN4TX/CAN1TX/GPIO[42]/PC[10] LIN6RX/WKUP[20]/E1UC[30]/E1UC[16]/GPIO[103]/PG[7] LIN6TX/E1UC[15]/GPIO[102]/PG[6] E0UC[30]/CAN0TX/GPIO[16]/PB[0] LIN0RX/CAN0RX/WKUP[4]/E0UC[31]/GPIO[17]/PB[1] CAN2RX/CAN3RX/WKUP[22]/CS5_0/E1UC[1]/GPIO[89]/PF[9] CAN2TX/CS4_0/CAN3TX/GPIO[88]/PF[8] LIN5TX/E1UC[25]/GPIO[92]/PF[12] E1UC[28]/LIN1TX/GPIO[38]/PC[6] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144LQFP pin configuration LIN1RX/WKUP[12]/E1UC[29]/GPIO[39]/PC[7] E1UC[2]/LIN4TX/CS1_0/GPIO[90]/PF[10] EMIOS[1]\LIN4RX/WKUP[15]/E1UC[3]/CS2_0/GPIO[91]/PF[11] WKUP[10]/E0UC[1]/SCK_0/CS0_0/GPIO[15]/PA[15] LIN5RX/WKUP[16]/E1UC[26]/GPIO[93]/PF[13] EIRQ[4]/E0UC[0]/CS0_0/SCK_0/GPIO[14]/PA[14] CSO_1\LIN5RX/WKUP[9]/E0UC[4]/GPIO[4]/PA[4] E0UC[29]/SOUT_0/GPIO[13]/PA[13] CS3_1\EIRQ[17]/SIN_0/E0UC[28]/GPIO[12]/PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV Note: Availability of port pin alternate functions depends on product selection. 144 LQFP Top view MPC5607B Microcontroller Data Sheet, Rev. 3 EIRQ[26]\ADC1_S[5]\OSC32K_EXTAL//WKUP[26]/ADC0_S[1]/GPIO[25]/PB[9] Figure 3. 144 LQFP pin configuration (top view) EIRQ[25]\OSC32K_XTAL//WKUP[25]/ANS[0]/GPIO[24]/PB[8] ADC1_S[6]\WKUP[8]/ADC0_S[2]/GPIO[26]/PB[10] ADC0_S[8]/CS3_1/E0UC[10]/GPIO[80]/PF[0] ADC0_S[9]/CS4_1/E0UC[11]/GPIO[81]/PF[1] ADC0_S[10]/CS0_2/E0UC[12]/GPIO[82]/PF[2] ADC0_S[11]/CS1_2/E0UC[13]/GPIO[83]/PF[3] ADC0_S[12]/CS2_2/E0UC[14]/GPIO[84]/PF[4] ADC0_S[13]/CS3_2/E0UC[22]/GPIO[85]/PF[5] ADC0_S[14]/CS1_1/E0UC[23]/GPIO[86]/PF[6] ADC0_S[15]/CS2_1/GPIO[87]/PF[7] EIRQ[27]\ANP[4]//WKUP[27]/GPIO[48]/PD[0] EIRQ[28]\ANP[5]/WKUP[28]/GPIO[49]/PD[1] ADC1_P[7]/ADC0_P[6]/GPIO[50]/PD[2] ADC1_P[7]/ADC0_P[7]/GPIO[51]/PD[3] ADC1_P[8]/ADC0_P[8]/GPIO[52]/PD[4] ADC1_P[9]/ADC0_P[9]/GPIO[53]/PD[5] ADC1_P[10]/ADC0_P[10]/GPIO[54]/PD[6] ADC1_P[11]/ADC0_P11]/GPIO[55]/PD[7] ADC1_P[12]/ADC0_P[12]/GPIO[56]/PD[8] ADC1_P[0]/ADC0_P[0]/GPIO[20]/PB[4] 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 Preliminary--Subject to Change Without Notice PA[11]/GPIO[11]/E0UC[11]/SCL/EIRQ[16]/LIN2RX/ADC1_S[3] PA[10]/GPIO[10]/E0UC[10]/SDA/LIN2TX/ADC1_S[2] PA[9]/GPIO[9]/E0UC[9]/FAB/CS2_1 PA[8]/GPIO[8]/E0UC[8]/E0UC[14]/EIRQ[3]/ABS[0]/LIN3RX PA[7]/GPIO[7]/E0UC[7]/LIN3TX/EIRQ[2]/ADC1_S[1] PE[13]/GPIO[77]/SOUT_2/E1UC[20] PF[14]/GPIO[94]/CAN4TX/E1UC[27]/CAN1TX PF[15]/GPIO[95]/E1UC[4]/EIRQ[13]/CAN4RX/CAN1RX VDD_HV VSS_HV PG[0]/GPIO[96]/CAN5TX/E1UC[23] PG[1]/GPIO[97]/E1UC[24]/EIRQ[14]/CAN5RX PH[3]/GPIO[115]/E1UC[5]/CS0_1 PH[2]/GPIO[114]/E1UC[4]/SCK_1 PH[1]/GPIO[113]/E1UC[3]/SOUT_1 PH[0]/GPIO[112]/E1UC[2]/SIN_1 PG[12]/GPIO[108]/E0UC[26]/SOUT_4 PG[13]/GPIO[109]/E0UC[27]/SCK_4 PA[3]/GPIO[3]/E0UC[3]/LIN5TX/EIRQ[0]/CS4_1/ADC1_S[0] PB[15]/GPIO[31]/E0UC[7]/CS4_0/ADC0_X[3] PD[15]/GPIO[63]/CS2_1/E0UC[27]/ADC0_S[7] PB[14]/GPIO[30]/E0UC[6]/CS3_ 0/ADC0_X[2] PD[14]/GPIO[62]/CS1_1/E0UC[26]/ADC0_S[6] PB[13]/GPIO[29]/E0UC[5]/CS2_0/ADC0_X[1] PD[13]/GPIO[61]/CS0_1/E0UC[25]/ADC0_S[5] /GPIO[28]/E0UC[4]/CS1_0 VDD_HV_ADC1 VSS_HV_ADC1 PD[11]/GPIO[59]/ADC0_P[15]/ADC1_P[15] PD[10]/GPIO[58]/ADC0_P[14]/ADC1_P[14] PD[9]/GPIO[57]/ADC0_P[13]/ADC1_P[13] PB[7]/GPIO[23]/ADC0_P[3]/ADC1_P[3] PB[6]/GPIO[22]/ADC0_P[2]/ADC1_P[2] PB[5]/GPIO[21]/ADC0_P[1]/ADC1_P[1] VDD_HV_ADC0 VSS_HV_ADC0 PB[2]/GPIO[18]/LIN0TX/SDA/E0UC[30] PC[8]/GPIO[40]/LIN2TX/E0UC[3] PC[13]/GPIO[45]/E0UC[13]/SOUT_2 PC[12]/GPIO[44]/E0UC[12]/EIRQ[19]/SIN_2 PE[7]/GPIO[71]/E0UC[23]/CS2_0/MA[0]/EIRQ[23] PE[6]/GPIO[70]/E0UC[22]/CS3_0/MA[1]/EIRQ[22] PH[8]/GPIO[120]/E1UC[10]/CS2_2/MA[0] PH[7]/GPIO[119]/E1UC[9]/CS3_2/MA[1] PH[6]/GPIO[118]/E1UC[8]/MA[2] PH[5]/GPIO[117]/E1UC[7] PH[4]/GPIO[116]/E1UC[6] PE[5]/GPIO[69]/E0UC[21]/CS0_1/MA[2] PE[4]/GPIO[68]/E0UC[20]/SCK_1/EIRQ[9] PC[4]/GPIO[36]/E1UC[31]/EIRQ[18]/SIN_1/CAN3RX PC[5]/GPIO[37]/SOUT_1/CAN3TX/EIRQ[7] PE[3]/GPIO[67]/E0UC[19]/SOUT_1 PE[2]/GPIO[66]/E0UC[18]/EIRQ[21]/SIN_1 PH[9]/GPIO[121]/TCK PC[0]/GPIO[32]/TDI VSS_LV VDD_LV VDD_HV VSS_HV PC[1]/GPIO[33]/TDO PH[10]/GPIO[122]/TMS PA[6]/GPIO[6]/E0UC[6]/EIRQ[1]/LIN4RX/CS1_1 PA[5]/GPIO[5]/E0UC[5]/LIN4TX PC[2]/GPIO[34]/SCK_1/CAN4TX/EIRQ[5] PC[3]/GPIO[35]/CS0_1/MA[0]/EIRQ[6]/CAN4RX/CAN1RX PG[11]/GPIO[107]/E0UC[25]/CS0_4 PG[10]/GPIO[106]/E0UC[24]/E1UC[31]/SIN_4 PE[15]/GPIO[79]/CS0_2/E1UC[22] PE[14]/GPIO[78]/SCK_2/E1UC[21]/EIRQ[12] PG[15]/GPIO[111]/E1UC[1]/LIN8RX PG[14]/GPIO[110]/E1UC[0]/LIN8TX PE[12]/GPIO[76]/E1UC[19]/EIRQ[11]/SIN_2\ANS[7] Package pinouts 9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Package pinouts 2.3 208MAPBGA pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A PC[8] PC[1 PH[1 PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[1 PH[1 3] 5] 5] 1] NC NC A B PC[9] PB[2] PH[1 PC[1 PE[6] PH[5] PC[4] PH[9] PH[1 PI[2] PC[3] PG[1 PG[1 PG[1 PA[1 PA[1 3] 2] 0] 1] 5] 4] 1] 0] PC[14 ] VDD_ HV B C PB[3] PE[7] PH[7] PE[5] PE[3] VSS_ PC[1] PI[3] PA[5] PI[5] PE[1 PE[1 PA[9] PA[8] LV 4] 2] NC PA[6] PH[1 PG[1 PF[1 PE[1 PA[7] 2] 0] 4] 3] PG[1] PG[0] PF[1 VDD 5] _HV PH[0] PH[1] PH[3] PH[2] VSS_ VSS_ VSS_ VSS_ HV HV HV HV VSS_ VSS_ VSS_ VSS_ HV HV HV HV VSS_ VSS_ VSS_ VSS_ HV HV HV HV VSS_ VSS_ VSS_ VSS_ HV HV HV HV VDD PI[12 PI[13 MSE _HV ] ] O MDO MDO MDO MDO 3 2 0 1 PI[8] PI[9] PI[10 PI[11 ] ] VDD PG[1 PA[3] PG[1 _HV_ 2] 3] ADC 1 PB[1 PD[1 PD[1 PB[1 5] 5] 4] 4] PB[1 PD[1 PD[1 PB[1 3] 3] 2] 2] C D PH[14 PI[6] PC[1 PI[7] PH[6] PE[4] PE[2] VDD VDD ] 5] _LV _HV PG[4] PG[5] PG[3] PG[2] PE[0] PA[2] PA[1] PE[1] PE[9] PE[8] PE[1 PA[0] 0] VSS_ PE[1 VDD HV 1] _HV RESE VSS_ NC T LV EVTI NC NC NC D E E F F G G H H J J K VDD VDD _BV _LV K L PG[9] PG[8] NC EVT O L M PG[7] PG[6] PC[1 PC[1 0] 1] M N PB[1] PF[9] PB[0] VDD PJ[0] PA[4] VSS_ EXTA VDD PF[0] PF[4] VSS_ PB[1 PD[1 PD[9] PD[1 _HV LV L _HV HV_ 1] 0] 1] ADC 1 PF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[1 VDD XTAL PB[1 PF[1] PF[5] PD[0] PD[3] VDD PB[6] PB[7] 4] _LV 0] _HV_ ADC 0 PF[12 PC[6] PF[1 PF[1 VDD PA[1 PA[1 PI[14 XTAL PF[3] PF[7] PD[2] PD[4] PD[7] VSS_ PB[5] ] 0] 1] _HV 5] 3] ] HV_ ADC 0 NC NC NC MCK O 4 N P P R R T NC PF[1 PA[1 PI[15 EXTA PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] 3] 2] ] L 6 7 8 9 10 11 12 13 14 15 16 T 1 2 3 5 NOTE: The 208 MAPBGA is available only as development package for Nexus 2+. NC = Not connected Figure 4. 208 MAPBGA configuration MPC5607B Microcontroller Data Sheet, Rev. 3 10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrical characteristics 3 Electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol "SR" for System Requirement is included in the Symbol column. CAUTION All of the following figures are indicative and must be confirmed during either silicon validation, silicon characterization or silicon reliability trial. 3.1 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where appropriate. Table 3. Parameter classifications Classification tag P C T Tag description Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. D NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate. 3.2 NVUSRO register Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register. 3.2.1 NVUSRO[PAD3V5V] field description Table 4 shows how NVUSRO[PAD3V5V] controls the device configuration. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11 Electrical characteristics Table 4. PAD3V5V field description1 Value2 0 1 1 2 Description Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages High voltage supply is 5.0 V High voltage supply is 3.3 V See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The DC electrical characteristics are dependent on the PAD3V5V bit value. 3.2.2 NVUSRO[OSCILLATOR_MARGIN] field description Table 5. OSCILLATOR_MARGIN field description1 Value2 0 1 Description Low consumption configuration (4 MHz/8 MHz) High margin configuration (4 MHz/16 MHz) Table 5 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. 1 2 See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The main external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. 3.2.3 NVUSRO[WATCHDOG_EN] field description Table 6. WATCHDOG_EN field description1 Value2 0 1 Disable after reset Enable after reset Description Table 5 shows how NVUSRO[WATCHDOG_EN] controls the device configuration. 1 2 See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. MPC5607B Microcontroller Data Sheet, Rev. 3 12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 3.3 Absolute maximum ratings Table 7. Absolute maximum ratings Symbol VSS SR Parameter Digital ground on VSS_HV pins Voltage on VDD_HV pins with respect to ground (VSS) Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) Voltage on VSS_HV_ADC 0, VSS_HV_ADC 1 (ADC reference) pin with respect to ground (VSS) Conditions Min -- 0 Max 0 V Unit Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 13 Preliminary--Subject to Change Without Notice Value VDD SR -- -0.3 6.0 V VSS_LV SR -- VSS-0.1 VSS+0.1 V VDD_BV SR -- Relative to VDD -0.3 -0.3 6.0 VDD+0.3 V VSS_ADC SR -- VSS-0.1 VSS+0.1 V VDD_ADC SR Voltage on -- VSS_HV_ADC Relative to VDD 0, VSS_HV_ADC 1 (ADC reference) with respect to ground (VSS) -- Voltage on any GPIO pin with Relative to VDD respect to ground (VSS) -0.3 VDD -0.3 6.0 VDD+0.3 V VIN SR -0.3 VDD -0.3 6.0 VDD+0.3 V MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics Table 7. Absolute maximum ratings (continued) Value Symbol IINJPAD SR Parameter Injected input current on any pin during overload condition Absolute sum of all injected input currents during overload condition Sum of all the static I/O current within a supply segment Conditions Min -- -10 Max 10 mA Unit Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages IINJSUM SR -- -50 50 IAVGSEG SR VDD = 5.0 V 10%, PAD3V5V =0 VDD = 3.3 V 10%, PAD3V5V =1 -- -55 70 mA 64 TSTORAGE SR Storage temperature 150 C NOTE Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values. 3.4 Recommended operating conditions Table 8. Recommended operating conditions (3.3 V) Value Symbol VSS VDD 1 Parameter SR Digital ground on VSS_HV pins SR Voltage on VDD_HV pins with respect to ground (VSS) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) Conditions Min -- -- -- 0 3.0 Max 0 3.6 Unit V V V VSS_LV2 VSS-0.1 VSS+0.1 VDD_BV3 -- Relative to VDD 3.0 3.6 V VDD-0.1 VDD+0.1 MPC5607B Microcontroller Data Sheet, Rev. 3 14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 8. Recommended operating conditions (3.3 V) (continued) Value Symbol VSS_ADC Parameter SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) pin with respect to ground (VSS) Conditions Min -- Max V VSS-0.1 VSS+0.1 Unit Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 15 Preliminary--Subject to Change Without Notice VDD_ADC4 -- SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) with Relative to VDD respect to ground (VSS) SR Voltage on any GPIO pin with respect to ground (VSS) SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition SR VDD slope to ensure correct power up6 SR Ambient temperature under bias SR Junction temperature under bias fCPU < 64 MHz -- -- Relative to VDD -- -- -- 3.05 3.6 V VDD-0.1 VDD+0.1 VSS-0.1 -- -5 -50 -- -40 -40 -- VDD+0.1 5 50 0.25 125 150 V/s C mA V VIN IINJPAD IINJSUM TVDD TA TJ 1 2 3 4 5 6 100 nF capacitance needs to be provided between each VDD/VSS pair 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. Guaranteed by device validation Table 9. Recommended operating conditions (5.0 V) Value Symbol VSS VDD1 VSS_LV3 VDD_BV4 Parameter SR Digital ground on VSS_HV pins SR Voltage on VDD_HV pins with respect to ground (VSS) Conditions Min -- -- Voltage SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) drop2 0 4.5 3.0 Max 0 5.5 5.5 V V V V Unit -- -- Voltage drop 2 VSS-0.1 VSS+0.1 4.5 3.0 5.5 5.5 Relative to VDD VDD-0.1 VDD+0.1 VSS_ADC SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) pin with respect to ground (VSS) -- VSS-0.1 VSS+0.1 V MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics Table 9. Recommended operating conditions (5.0 V) (continued) Value Symbol Parameter Conditions Min VDD_ADC5 SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) with respect to ground (VSS) -- Voltage drop 2 Unit 4.5 3.0 5.5 5.5 V Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Max Relative to VDD VDD-0.1 VDD+0.1 VIN SR Voltage on any GPIO pin with respect to ground (VSS) -- Relative to VDD IINJPAD IINJSUM TVDD SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition SR VDD slope to ensure correct power up6 -- -- -- -- TA C-Grade SR Ambient temperature under bias Part VSS-0.1 -5 -50 -- 3 -40 -40 -40 -40 -40 -40 VDD+0.1 5 50 0.25 -- 85 110 105 130 125 150 V mA V/s V/s C fCPU < 64 MHz -- fCPU < 64 MHz -- fCPU < 60 MHz -- TJ C-Grade SR Junction temperature under bias Part TA V-Grade SR Ambient temperature under bias Part TJ V-Grade SR Junction temperature under bias Part TA M-Grade SR Ambient temperature under bias Part TJ M-Grade SR Junction temperature under bias Part 1 2 3 4 5 6 100 nF capacitance needs to be provided between each VDD/VSS pair Full device operation is guaranteed by design when the voltage drops below 4.5V down to 3.6V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). This decoupling need to be increased as recommended in Section 3.5.1, "External ballast resistor recommendations incase external ballast resistor is planned to be used. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair Guaranteed by device validation NOTE RAM data retention is guaranteed wi`th VDD_LV not below 1.08 V. MPC5607B Microcontroller Data Sheet, Rev. 3 16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 3.5 3.5.1 Thermal characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages External ballast resistor recommendations External ballast resistor on VDD_BV pin helps in reducing the overall power dissipation inside the device. This resistor is required only when maximum power consumption exceeds the limit imposed by package thermal characteristics. As stated in Table 10 LQFP thermal characteristics, considering thermal resistance of LQFP144 as 48.3 C/W, at ambient TA = 125 C, the junction temp Tj will cross 150 C if total power dissipation > (150 - 125)/48.3 = 517 mW. Therefore, total device current IDDMAX at 125 C/5.5V must not exceed 94.1 mA (i.e. PD/VDD). Assuming an average IDD(VDD_HV) of 15-20 mA consumption typically during device RUN mode, the LV domain consumption IDD(VDD_BV) is thus limited to IDDMAX IDD(VDD_HV) i.e. 80 mA. Therefore, respecting the maximum power allowed as explained in Section 3.5.2, "Package thermal characteristics, it is recommended to use this resistor only in the 125 C/5.5V operating corner as per the following guidelines: * * * If IDD(VDD_BV) < 80 mA, then no resistor is required. If 80 mA < IDD(VDD_BV) < 90 mA, then 4 Ohm resistor can be used along with 14.7 f decoupling. If IDD(VDD_BV) > 90 mA, then 8 Ohm resistor can be used along with 33 f decoupling. Using resistance in the range of 4-8 Ohm, the gain will be around 10-20% of total consumption on VDD_BV. For example, if 8 Ohm resistor is used, then power consumption when IDD(VDD_BV) is 110 mA is equivalent to power consumption when IDD(VDD_BV) is 90 mA (approximately) when resistor not used. 3.5.2 Package thermal characteristics Table 10. LQFP thermal characteristics1 Symbol C CC D Parameter Conditions2 Value3 Pin count Min Typ -- -- -- Max 64 64 64 C/W 100 144 176 -- -- -- Unit RJA Single-layer Thermal resistance, board--1s junction-toambient natural convection4 Four-layer board--2s2p 100 144 176 -- -- -- -- -- -- 49.7 48.3 47.3 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C. 3 All values need to be confirmed during device validation. 4 Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA. 2 MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17 Electrical characteristics Table 11. 208 MAPBGA thermal characteristics1 Symbol RJA CC C -- Parameter Thermal resistance, junction-to-am bient natural convection2 Conditions Single-layer board--1s Four-layer board--2s2p Value TBD Unit Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages C/W 1 2 Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA. 3.5.3 Power considerations TJ = TA + (PD x RJA) Where: TA is the ambient temperature in C. RJA is the package junction-to-ambient thermal resistance, in C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. Eqn. 1 The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1: Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273 C) Therefore, solving equations 1 and 2: K = PD x (TA + 273 C) + RJA x PD2 Eqn. 3 Eqn. 2 Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any value of TA. 3.6 3.6.1 * * I/O pad electrical characteristics I/O pad types Slow pads - are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads - provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. MPC5607B Microcontroller Data Sheet, Rev. 3 The device provides four main I/O pad types depending on the associated alternate functions: 18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics * * Fast pads - provide maximum speed. These are used for improved Nexus debugging capability. Input only pads - are associated with ADC channels and 32 kHz low power external crystal oscillator providing low input leakage. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance. 3.6.2 I/O input DC characteristics Table 12 provides input DC electrical characteristics as described in Figure 5. VIN VDD VIH VHYS VIL PDIx = `1 (GPDI register of SIUL) PDIx = `0' Figure 5. I/O input DC electrical characteristics definition Table 12. I/O input DC electrical characteristics Symbol VIH VIL C Parameter Conditions1 Min SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger) -- -- -- 0.65VDD -0.4 0.1VDD Value2 Unit Typ -- -- -- Max VDD+0.4 0.35VDD -- V VHYS CC C Input hysteresis CMOS (Schmitt Trigger) MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19 Electrical characteristics Table 12. I/O input DC electrical characteristics (continued) Symbol C Parameter Conditions No injection on adjacent pin 1 Value2 Unit -- -- -- -- -- 1000 2 2 12 70 -- -- -- -- 500 1000 40 -- ns ns nA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Min Typ Max ILKG CC P Digital input leakage P D P WFI SR P Width of input pulse surely filtered by analog filter3 TA = -40 C TA = 25 C TA = 105 C TA = 125 C -- -- WNFI SR P Width of input pulse surely not filtered by analog filter3 1 2 VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation. 3 Analog filters are available on all wakeup lines. MPC5607B Microcontroller Data Sheet, Rev. 3 20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 3.6.3 * * * * I/O output DC characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 21 Preliminary--Subject to Change Without Notice The following tables provide DC characteristics for bidirectional pads: Table 13 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 15 provides output driver characteristics for I/O pads when in SLOW configuration. Table 16 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 14 provides output driver characteristics for I/O pads when in FAST configuration. Table 13. I/O pull-up/pull-down DC electrical characteristics Symbol |IWPU| CC C P C P Parameter Weak pull-up current absolute value Conditions1 Min VIN = VIL, PAD3V5V VDD = =0 5.0 V PAD3V5V 10% = 12 VIN = VIL, PAD3V5V VDD = =1 3.3 V 10% Weak pull-down current absolute value VIN = VIH, PAD3V5V =0 VDD = 5.0 V PAD3V5V 10% =1 VIN = VIH, PAD3V5V VDD = =1 3.3 V 10% 10 10 10 Value Unit Typ -- -- -- Max 150 250 150 A |IWPD| CC P C P 10 10 10 -- -- -- 150 250 150 A 1 2 VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics Table 14. FAST configuration output buffer electrical characteristics Symbol VOH CC C P Parameter Conditions1 Min Output Push Pull high level FAST configurati on IOH = -14mA, VDD = 5.0 V 10%, PAD3V5V =0 (recomme nded) IOH = -7mA, VDD = 5.0 V 10%, PAD3V5V = 12 IOH = -11mA, VDD = 3.3 V 10%, PAD3V5V =1 (recomme nded) Output low Push Pull level FAST configurati on IOL = 14mA, VDD = 5.0 V 10%, PAD3V5V =0 (recomme nded) IOL = 7mA, VDD = 5.0 V 10%, PAD3V5V = 12 IOL = 11mA, VDD = 3.3 V 10%, PAD3V5V =1 (recomme nded) 0.8VDD Value Unit -- -- V Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Typ Max C 0.8VDD -- -- C VDD-0.8 -- -- VOL CC P -- -- 0.1VDD V C -- -- 0.1VDD C -- -- 0.5 MPC5607B Microcontroller Data Sheet, Rev. 3 22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 1 2 VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 3.6.4 Output pin transition times Table 15. Output pin transition times Symbol Ttr CC C D T D D T D Ttr CC D T D D T D Output transition time output pin3 MEDIUM configurati on Parameter Output transition time output pin3 SLOW configurati on Conditions CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF VDD = 5.0 V 10%, PAD3V5V =0 SIUL.PCR x.SRC = 1 VDD = 3.3 V 10%, PAD3V5V =1 SIUL.PCR x.SRC = 1 VDD = 3.3 V 10%, PAD3V5V =1 1 Value2 Unit Min Typ -- -- -- -- -- -- -- -- -- -- -- -- Max 50 100 125 50 100 125 10 20 40 12 25 40 ns ns -- -- -- -- -- -- -- -- -- -- -- -- VDD = 5.0 V 10%, PAD3V5V =0 MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrical characteristics Table 15. Output pin transition times (continued) Symbol Ttr CC C D Parameter Output transition time output pin3 FAST configurati on Conditions CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF 1 2 1 Value2 Unit -- -- -- -- -- -- -- -- -- 4 6 12 4 7 12 ns Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Min Typ Max VDD = 5.0 V 10%, PAD3V5V =0 VDD = 3.3 V 10%, PAD3V5V =1 -- -- -- VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation. 3 C includes device and package capacitances (C L PKG < 5 pF). 3.6.5 I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 16. Table 17 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value. Table 16. I/O supply segments Supply segment Package 1 208 MAPBGA1 176 LQFP pin7- pin27 144 LQFP 100 LQFP 1 2 3 4 5 6 7 MCKO pin124 - pin150 8 MDOn /MSEO pin151 - pin6 -- -- Equivalent to 176 LQFP segment pad distribution pin28 - pin57 pin51 - pin99 pin37 - pin69 pin59 - pin85 pin100 - pin122 pin70 - pin83 pin86 - pin123 pin 123 - pin19 pin84 - pin15 -- -- -- -- pin20 - pin49 pin16 - pin35 -- -- 208 MAPBGA available only as development package for Nexus2+ MPC5607B Microcontroller Data Sheet, Rev. 3 24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 17. I/O consumption Symbol IDYNSEG SR C D Parameter Sum of all the dynamic and static I/O current within a supply segment Conditions1 Min VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 -- -- Value2 Unit -- -- 110 65 mA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 25 Preliminary--Subject to Change Without Notice Typ Max ISWTSLW,3 CC D Dynamic CL = I/O current 25 pF for SLOW configurati on VDD = 5.0 V 10%, PAD3V5V =0 VDD = 3.3 V 10%, PAD3V5V =1 -- -- 20 mA -- -- 16 ISWTMED3 CC D Dynamic CL = I/O current 25 pF for MEDIUM configurati on VDD = 5.0 V 10%, PAD3V5V =0 VDD = 3.3 V 10%, PAD3V5V =1 VDD = 5.0 V 10%, PAD3V5V =0 VDD = 3.3 V 10%, PAD3V5V =1 -- -- 29 mA -- -- 17 ISWTFST3 CC D Dynamic CL = I/O current 25 pF for FAST configurati on -- -- 110 mA -- -- 50 MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics Table 17. I/O consumption (continued) Symbol IRMSSLW CC C D Parameter Root medium square I/O current for SLOW configurati on Conditions CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz CL = 100 pF, 2 MHz CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz CL = 100 pF, 2 MHz IRMSMED CC D Root medium square I/O current for MEDIUM configurati on CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz CL = 100 pF, 13 MHz CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz CL = 100 pF, 13 MHz VDD = 3.3 V 10%, PAD3V5V =1 VDD = 5.0 V 10%, PAD3V5V =0 VDD = 3.3 V 10%, PAD3V5V =1 1 Value2 Unit -- -- 2.3 mA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Min Typ Max VDD = 5.0 V 10%, PAD3V5V =0 -- -- 3.2 -- -- 6.6 -- -- 1.6 -- -- 2.3 -- -- 4.7 -- -- 6.6 mA -- -- 13.4 -- -- 18.3 -- -- 5 -- -- 8.5 -- -- 11 MPC5607B Microcontroller Data Sheet, Rev. 3 26 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 17. I/O consumption (continued) Symbol IRMSFST CC C D Parameter Root medium square I/O current for FAST configurati on Conditions CL = 25 pF, 40 MHz CL = 25 pF, 64 MHz CL = 100 pF, 40 MHz CL = 25 pF, 40 MHz CL = 25 pF, 64 MHz CL = 100 pF, 40 MHz IAVGSEG SR D Sum of all the static I/O current within a supply segment VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 3.3 V 10 %, PAD3V5V =1 1 Value2 Unit -- -- 22 mA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 27 Min Typ Max VDD = 5.0 V 10%, PAD3V5V =0 -- -- 33 -- -- 56 -- -- 14 -- -- 20 -- -- 35 -- -- -- -- 70 65 mA VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to125 C, unless otherwise specified All values need to be confirmed during device validation. 3 Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. 1 2 3.7 nRSTIN electrical characteristics The device implements a dedicated bidirectional RESET pin. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice Electrical characteristics VDD nRSTIN VIH VIL device reset forced by nRSTIN device start-up phase Figure 6. Start-up reset requirements VRSTIN hw_rst VDD `1' VIH VIL `0' filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter WFRST WNFRST unknown reset state device under hardware reset Figure 7. Noise filtering on reset signal MPC5607B Microcontroller Data Sheet, Rev. 3 28 Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages VDDMIN Electrical characteristics Table 18. Reset electrical characteristics Symbol VIH VIL VHYS VOL C Parameter Conditions1 Min SR P Input High Level CMOS (Schmitt Trigger) SR P Input low Level CMOS (Schmitt Trigger) CC C Input hysteresis CMOS (Schmitt Trigger) CC P Output low level -- -- -- Push Pull, IOL = 2mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) Push Pull, IOL = 1mA, VDD = 5.0 V 10%, PAD3V5V = 13 Push Pull, IOL = 1mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) Ttr CC D Output transition time output pin4 MEDIUM configuration CL = 25pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 50pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 100pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 50pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100pF, VDD = 3.3 V 10%, PAD3V5V = 1 WFRST SR P nRSTIN input filtered pulse WNFRST SR P nRSTIN input not filtered pulse |IWPU| CC P Weak pull-up current absolute value -- -- VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 5.0 V 10%, PAD3V5V = 15 1 2 Value2 Unit 0.65VDD -0.4 0.1VDD -- -- -- -- -- VDD+0.4 0.35VDD -- 0.1VDD V V V V Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 29 Typ Max -- -- -- -- 0.1VDD 0.5 -- -- -- -- -- -- -- 1000 10 10 10 -- -- -- -- -- -- -- -- -- -- -- 10 20 40 12 25 40 40 -- 150 150 250 ns ns ns A VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation. 3 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the device reference manual). 4 CL includes device and package capacitance (CPKG < 5 pF). 5 The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice Electrical characteristics 3.8 3.8.1 Power management electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Voltage regulator electrical characteristics The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved: * * * HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD power pin. BV: High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV power pin. Voltage values should be aligned with VDD. LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the internal voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure noise isolation between critical LV modules within the device: -- LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. -- LV_CFLA: Low voltage supply for code Flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. -- LV_DFLA: Low voltage supply for data Flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. -- LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding. CREG2 (LV_COR/LV_CFLA) GND VDD VSS_LV VDD_LV VDD_BV VREF CDEC1 (Ballast decoupling) CREG1 (LV_COR/LV_DFLA) VDD_BV VDD_LV VDD_LVn Voltage Regulator DEVICE I VSS_LV VSS_LV VDD_LV VSS VDD VSS_LVn GND DEVICE GND GND CREG3 (LV_COR/LV_PLL) CDEC2 (supply/IO decoupling) Figure 8. Voltage regulator capacitance connection The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH. MPC5607B Microcontroller Data Sheet, Rev. 3 30 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see Section 3.4, "Recommended operating conditions). Table 19. Voltage regulator electrical characteristics Symbol CREGn RREG CDEC1 CDEC2 VMREG C Parameter Conditions1 Min SR -- Internal voltage regulator external capacitance SR -- Stability capacitor equivalent serial resistance SR -- Decoupling capacitance3,4 ballast SR -- Decoupling capacitance regulator supply CC P Main regulator output voltage -- -- VDD_BV/VSS_LV pair VDD/VSS pair Before trimming After trimming IMREG IMREGINT SR -- Main regulator current provided to VDD_LV domain CC D Main regulator module current consumption CC P Low power regulator output voltage SR -- Low power regulator current provided to VDD_LV domain -- IMREG = 200 mA IMREG = 0 mA After trimming -- 200 -- 400 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Value2 Unit Typ -- -- 4705 100 1.32 1.28 -- -- -- 1.23 -- -- 5 1.23 -- -- 2 17 Max 330 0.2 -- -- -- -- 150 2 1 -- 15 600 TBD -- 5 100 TBD -- A V mA A V mA A mA mA nF W nF nF V VLPREG ILPREG ILPREGINT CC D Low power regulator module current ILPREG = 15 mA; consumption TA = 55 C -- ILPREG = 0 mA; TA = 55 C Post trimming -- IULPREG = 5 mA; TA = 55 C IULPREG = 0 mA; TA = 55 C VULPREG IULPREG IULPREGINT CC P Ultra low power regulator output voltage SR -- Ultra low power regulator current provided to VDD_LV domain CC D Ultra low power regulator module current consumption IVREGREF CC D Main LVDs and reference current consumption (low power and main regulator switched off) CC D Main LVD current consumption (switch-off during standby) CC D In-rush current on VDD_BV during power-up TA = 55 C IVREDLVD12 IDD_BV 1 2 TA = 55 C -- -- -- 2 -- TBD 4006 A mA VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrical characteristics 3 MPC5607B Microcontroller Data Sheet, Rev. 3 32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical value is in the range of 470 nF. 4 In case external ballast resistor is planned to be used, then to avoid a LVD reset during standby mode exit, the following configuration need to be respected. - for 8 ohm ballast resistor, decoupling cap of 33 f is required. - for 4 ohm ballast resistor, decoupling cap of 14.7f is required. These values are only after preliminary validation and are subject to change. 5 External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in operating range. 6 In-rush current is seen only for short time during power-up and on standby exit (max 20s, depending on external capacitances to be load) Electrical characteristics 3.8.2 Voltage monitor electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 33 Preliminary--Subject to Change Without Notice The device implements a Power-on Reset module to ensure correct power-up initialization, as well as four low voltage detectors to monitor the VDD and the VDD_LV voltage while device is supplied: * * * * * * POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state LVDHV3 monitors VDD to ensure device reset below minimum functional supply LVDHV3B monitors VDD_BV to ensure device reset below minimum functional supply LVDHV5 monitors VDD when application uses device in the 5.0 V 10% range LVDLVCOR monitors power domain No. 1 LVDLVBKP monitors power domain No. 0 NOTE When enabled, power domain No. 2 is monitored through LVD_DIGBKP. VDD VLVDHVxH VLVDHVxL RESET Figure 9. Low voltage monitor vs reset MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics Table 20. Low voltage monitor electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Symbol VPORUP SR C P Parameter Condition s1 1.0 Value2 -- 5.5 Unit V Symbol VPORUP Supply for TA = 25 C, functional after POR trimming module Power-on reset threshold LVDHV3 low voltage detector high threshold LVDHV3 low voltage detector low threshold LVDHV3B low voltage detector high threshold LVDHV3B L low voltage detector low threshold LVDHV5 low voltage detector high threshold LVDHV5 low voltage detector low threshold LVDLVCO R low voltage detector low threshold VPORH CC P 1.5 -- 2.6 VPORH VLVDHV3H CC T -- -- 2.95 VLVDHV3H VLVDHV3L CC P 2.7 -- 2.9 VLVDHV3L VLVDHV3BH CC P -- -- 2.95 VLVDHV3BH VLVDHV3BL CC P 2.7 -- 2.9 VLVDHV3BL VLVDHV5H CC T -- -- 4.5 VLVDHV5H VLVDHV5L CC P 3.8 -- 4.4 VLVDHV5L VLVDLVCOR L CC P 1.07 -- 1.11 VLVDLVCOR L 1 VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified MPC5607B Microcontroller Data Sheet, Rev. 3 34 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 2 All values need to be confirmed during device validation. 3.9 Low voltage domain power consumption Table 21. Low voltage power domain electrical characteristics Symbol IDDMAX2 CC C D Parameter RUN mode maximum average current RUN mode typical average current5 HALT mode current6 STOP mode current7 Slow internal RC oscillator (128 kHz) running Conditions1 Min -- -- Value Unit Typ 115 Max 1403 mA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 35 Preliminary--Subject to Change Without Notice Table 21 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. IDDRUN4 CC T P -- -- -- -- 80 TBD 100 TBD mA IDDHALT CC P -- -- 8 TBD mA IDDSTOP CC P D D D P TA = 25 C TA = 55 C TA = 85 C TA = 105 C TA = 125 C -- -- -- -- -- -- -- -- -- -- 350 750 2 4 9 30 TBD 9008 -- -- -- TBD8 100 -- -- -- TBD A mA IDDSTDBY2 CC P D D D P STANDBY Slow 2 mode internal current9 RC oscillator (128 kHz) running TA = 25 C TA = 55 C TA = 85 C TA = 105 C TA = 125 C A MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics Table 21. Low voltage power domain electrical characteristics (continued) Symbol IDDSTDBY1 CC C T D D D D 1 2 Parameter Conditions1 Min TA = 25 C TA = 55 C TA = 85 C TA = 105 C TA = 125 C -- -- -- -- -- Value Unit 20 TBD 60 -- -- -- 280 TBD A Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Typ Max STANDBY Slow 1 mode internal current10 RC oscillator (128 kHz) running VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible. 3 Higher current may be sinked by device during power-up and standby exit. please refer to in rush current on Table 19. 4 RUN current measured with typical application with accesses on both flash and RAM. 5 Only for the "P" classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPi as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer reset enabled. 6 Data Flash Power Down. Code Flash in Low Power. RC-osc128kHz & RC-OSC 16MHz on. 10MHz XTAL clock. FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex: instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON (16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20KHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but not conversion except 2 analogue watchdog 7 Only for the "P" classification: No clock, RC 16MHz off, RC128kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode. 8 When going from RUN to STOP mode and the core consumption is > 6 mA , it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures exceeding 125 C and under these circumstances , it is possible for the current to initially exceed the maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA. 9 Only for the "P" classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum consumption, all possible modules switched-off. 10 ULPreg on, HP/LPVreg off, 8KB RAM on, device configured for minimum consumption, all possible modules switched-off. MPC5607B Microcontroller Data Sheet, Rev. 3 36 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 3.10 3.10.1 Flash memory electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 37 Preliminary--Subject to Change Without Notice Program/Erase characteristics Table 22 shows the program and erase characteristics. Table 22. Program and erase specifications Value Symbol C Parameter Min Tdwprogram CC C Double word (64 bits) program time4 16 KB block pre-progra m and erase time 32 KB block pre-progra m and erase time 128 KB block pre-progra m and erase time -- Typ1 22 Initial max2 TBD Max3 500 Unit s T16Kpperase -- 300 500 5000 ms T32Kpperase -- 400 600 5000 ms T128Kpperas e -- 800 1300 7500 ms Typical program and erase times assume nominal supply values and operation at 25 C. All times are subject to change pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 C, typical supply voltage. 3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead. 1 MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics Table 23. Flash module life Value Min P/E CC C Number of program/erase cycles per block for 16 Kbyte blocks over the operating temperature range (TJ) CC C Number of program/erase cycles per block for 32 Kbyte blocks over the operating temperature range (TJ) CC C Number of program/erase cycles per block for 128 Kbyte blocks over the operating temperature range (TJ) -- 100,000 Typ -- cycles Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Symbol C Parameter Conditions Unit P/E -- 10,000 100,0001 cycles P/E -- 1,000 100,0001 cycles Retention CC C Minimum data retention at 85 C average ambient temperature2 Blocks with 0-1,000 P/E cycles Blocks with 10,000 P/E cycles Blocks with 100,000 P/E cycles 20 10 5 -- -- -- years years years 1 2 To be confirmed Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range. ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. Table 24. Flash read access timing Symbol fREAD CC C P C C 1 Parameter Maximum frequency for Flash reading Conditions1 2 wait states 1 wait state 0 wait states Max 64 40 20 Unit MHz VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified 3.10.2 Flash power supply DC characteristics Table 25 shows the power supply DC characteristics on external supply. MPC5607B Microcontroller Data Sheet, Rev. 3 38 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 25. Flash power supply DC electrical characteristics Symbol ICFREAD3 IDFREAD3 CC Parameter Sum of the current consumptio n on VDDHV and VDDBV on read access Sum of the current consumptio n on VDDHV and VDDBV on matrix modificatio n (program/er ase) Sum of the current consumptio n on VDDHV and VDDBV during Flash low power mode Sum of the current consumptio n on VDDHV and VDDBV during Flash power down mode Conditions1 Min Flash module read fCPU = 64 MHz4 Code Flash Data Flash Value2 Unit 33 33 mA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 39 Preliminary--Subject to Change Without Notice Typ Max ICFMOD3 IDFMOD3 CC Program/ Erase on-going while reading Flash registers fCPU = 64 MHz4 Code Flash Data Flash 52 33 mA ICFLPW3 IDFLPW3 CC Code Flash Data Flash 1.1 900 mA A ICFPWD3 IDFPWD 3 CC Code Flash Data Flash 150 150 A 1 VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 / 125 C, unless otherwise specified All values need to be confirmed during device validation. 3 Data based on characterization results, not tested in production 4 fCPU 64 MHz can be achieved only at up to 105 C 2 MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics 3.10.3 Start-up/Switch-off timings Table 26. Start-up time/Switch-off time Symbol C T Parameter Conditions1 Min Delay for Flash module to exit reset mode Delay for Flash module to exit low-power mode Delay for Flash module to exit power-dow n mode Delay for Flash module to enter low-power mode Delay for Flash module to enter power-dow n mode -- -- Unit Typ -- Max 125 s Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Value TFLARSTEXI CC T TFLALPEXIT CC T -- -- -- 0.5 TFLAPDEXIT CC T -- -- -- 30 TFLALPENTR CC Y T -- -- -- 0.5 TFLAPDENT CC RY T -- -- -- 1.5 1 VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified 3.11 Electromagnetic compatibility (EMC) characteristics Susceptibility tests are performed on a sample basis during product characterization. 3.11.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for the application. * Software recommendations - The software flowchart must include the management of runaway conditions such as: -- Corrupted program counter MPC5607B Microcontroller Data Sheet, Rev. 3 40 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics * 3.11.2 Electromagnetic interference (EMI) The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC61967-1 standard, which specifies the general conditions for EMI measurements. Table 27. EMI radiated emission measurement1,2 Symbol -- fCPU VDD_LV SR SR SR C -- -- -- Paramete r Scan range Operating frequency LV operating voltages Peak level VDD = 5 V, TA = 25 C, LQFP144 package Test conformin g to IEC 61967-2, fOSC = 8 MHz/fCPU = 64 MHz Value Conditions Min -- -- -- 0.150 -- -- 64 1.28 Typ Max 1000 -- -- MHz MHz V Unit SEMI CC T No PLL frequency modulatio n 2% PLL frequency modulatio n -- -- 18 dBV -- -- 143 dBV EMI testing and I/O port waveforms per IEC 61967-1, -2, -4 For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local marketing representative. 3 All values need to be confirmed during device validation 2 1 3.11.3 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 41 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages -- Unexpected reset -- Critical data corruption (control registers...) Prequalification trials - Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. Electrical characteristics 3.11.3.1 Electrostatic discharge (ESD) Table 28. ESD absolute maximum ratings1,2 Symbol Ratings Conditions TA = 25 C conforming to AEC-Q100-002 TA = 25 C conforming to AEC-Q100-003 TA = 25 C conforming to AEC-Q100-011 Class H1C M2 C3A Max value3 2000 200 500 750 (corners) Unit V VESD(HBM) Electrostatic discharge voltage (Human Body Model) VESD(MM) Electrostatic discharge voltage (Machine Model) VESD(CDM) Electrostatic discharge voltage (Charged Device Model) 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3 Data based on characterization results, not tested in production 3.11.3.2 * * Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. Table 29. Latch-up results Symbol LU Parameter Static latch-up class Conditions TA = 125 C conforming to JESD 78 Class II level A These tests are compliant with the EIA/JESD 78 IC latch-up standard. 3.12 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics The device provides an oscillator/resonator driver. Figure describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. Table 30 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations. MPC5607B Microcontroller Data Sheet, Rev. 3 42 Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 partsx(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. Electrical characteristics EXTAL C1 Crystal EXTAL RP XTAL DEVICE VDD C2 I R EXTAL XTAL Resonator DEVICE XTAL DEVICE Figure 10. Crystal oscillator and resonator connection scheme NOTE XTAL/EXTAL must not be directly used to drive external circuits. Table 30. Crystal description Crystal equivalent series resistance ESR 300 300 150 120 120 Crystal motional capacitance (Cm) fF 2.68 2.46 2.93 3.11 3.90 Crystal motional inductance (Lm) mH 591.0 160.7 86.6 56.5 25.3 Load on xtalin/xtalout C1 = C2 (pF)1 21 17 15 15 10 Shunt capacitance between xtalout and xtalin C02 (pF) 2.93 3.01 2.91 2.93 3.00 Nominal frequency (MHz) NDK crystal reference 4 8 10 12 16 1 NX8045GB NX5032GA The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package, etc.). MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 43 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrical characteristics S_MTRANS bit (ME_GS register) 1 0 VXTAL VMXOSC VMXOSCOP 10% TMXOSCSU valid internal clock 1/fMXOSC 90% Figure 11. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Table 31. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Symbol fFXOSC gmFXOSC C Parameter Conditions1 Min SR -- Fast external crystal oscillator frequency CC C Fast external crystal oscillator transconductance CC P -- VDD = 3.3 V 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 0 VDD = 5.0 V 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 0 VDD = 3.3 V 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 1 VDD = 5.0 V 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 1 fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 VFXOSCOP CC P Oscillation operating point IFXOSC,3 CC T Fast external crystal oscillator consumption -- -- 4.0 2.2 Value2 Unit Typ -- -- Max 16.0 8.2 MHz mA/V 2.0 -- 7.4 CC C 2.7 -- 9.7 CC C 2.5 -- 9.2 VFXOSC CC T Oscillation amplitude at EXTAL 1.3 1.3 -- -- -- -- 0.95 2 -- -- V V 3 mA MPC5607B Microcontroller Data Sheet, Rev. 3 44 Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrical characteristics Table 31. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued) Symbol TFXOSCSU C Parameter Conditions 1 Value2 Unit -- -- 0.65VDD -0.4 -- -- -- -- 6 1.8 VDD+0.4 0.35VDD V V ms Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Min Typ Max CC T Fast external crystal oscillator start-up time fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 VIH VIL 1 2 SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger) Oscillator bypass mode Oscillator bypass mode VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation. 3 Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals) 3.13 Slow external crystal oscillator (32 kHz) electrical characteristics The device provides a low power oscillator/resonator driver. OSC32K_EXTAL C1 RP OSC32K_EXTAL Resonator OSC32K_XTAL C2 OSC32K_XTAL DEVICE Crystal DEVICE Figure 12. Crystal oscillator and resonator connection scheme NOTE OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 45 Electrical characteristics l C0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages C1 Crystal C2 C1 Cm Rm Lm C2 Figure 13. Equivalent circuit of a quartz crystal Table 32. Crystal motional characteristics1 Value Symbol Lm Cm Parameter Motional inductance Motional capacitance Conditions Min -- -- -- AC coupled @ C0 = 2.85 pF4 AC coupled @ C0 = 4.9 AC coupled @ C0 = 7.0 pF4 pF4 -- -- 18 -- -- -- -- Typ 11.796 2 -- -- -- -- -- Max -- -- 28 65 50 35 30 KH fF pF kW Unit C1/C2 Load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground2 Rm3 Motional resistance AC coupled @ C0 = 9.0 pF4 1 2 The crystal used is Epson Toyocom MC306. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It includes all the parasitics due to board traces, crystal and package. 3 Maximum ESR (R ) of the crystal is 50 k m 4 C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins MPC5607B Microcontroller Data Sheet, Rev. 3 46 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics OSCON bit (OSC_CTL register) 1 0 VOSC32K_XTAL VLPXOSC32K 90% 1/fLPXOSC32K 10% TLPXOSC32KSU valid internal clock Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics Table 33. Slow external crystal oscillator (32 kHz) electrical characteristics Symbol fSXOSC gmSXOSC C Parameter Conditions1 Min SR -- Slow external crystal oscillator frequency CC -- Slow external crystal oscillator transconductance -- VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10% PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 0 VSXOSC CC T Oscillation amplitude -- -- -- -- -- -- -- 32 Value2 Unit Typ 32.768 TBD TBD TBD TBD 2.1 TBD -- -- 8 23 -- V A A s Max 40 kHz mA/V ISXOSCBIAS CC T Oscillation bias current ISXOSC TSXOSCSU 1 CC T Slow external crystal oscillator consumption CC T Slow external crystal oscillator start-up time VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation. 3 Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal 2 MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 47 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrical characteristics 3.14 FMPLL electrical characteristics Table 34. FMPLL electrical characteristics Symbol fPLLIN C Parameter Conditions -- -- -- -- -- Stable oscillator (fPLLIN = 16 MHz) fPLLIN = 16 MHz (resonator), fPLLCLK @ 64 MHz, 4000 cycles TA = 25 C -- -- 1 The device provides a frequency modulated phase locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Value2 Unit Min Typ -- -- -- -- -- 40 -- -- Max 64 60 64 644 150 100 10 4 MHz % MHz MHz MHz s ns mA 4 40 16 -- 20 SR -- FMPLL reference clock3 SR -- FMPLL reference clock duty cycle3 PLLIN fPLLOUT CC P FMPLL output clock frequency fCPU fFREE tLOCK SR -- System clock frequency CC P Free-running frequency CC P FMPLL lock time tLTJIT CC -- FMPLL long term jitter IPLL 1 2 CC C FMPLL consumption VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified. All values need to be confirmed during device validation. 3 PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 4f CPU 64 MHz can be achieved only at up to 105 C 3.15 Fast internal RC oscillator (16 MHz) electrical characteristics Table 35. Fast internal RC oscillator (16 MHz) electrical characteristics Symbol fFIRC 3, The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up of the device. C Parameter Conditions1 Min -- 12 -- Value2 Unit Typ 16 Max -- 20 -- 200 A MHz CC P Fast internal RC oscillator high TA = 25 C, trimmed frequency SR -- -- CC T Fast internal RC oscillator high TA = 25 C, trimmed frequency current in running mode CC D Fast internal RC oscillator high TA = 25 C frequency current in power -- TA = 55 C down mode IFIRCRUN IFIRCPWD -- -- TBD TBD 10 TBD A MPC5607B Microcontroller Data Sheet, Rev. 3 48 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 35. Fast internal RC oscillator (16 MHz) electrical characteristics (continued) Symbol C Parameter Conditions 1 Value2 Unit -- -- -- -- -- -- -- -- -- -1 500 600 700 900 1250 1.1 1.2 -- -- -- -- -- -- -- -- 2.0 TBD 2.0 TBD +1 % s A Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Min Typ Max IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 C frequency and system clock current in stop mode sysclk = off sysclk = 2 MHz sysclk = 4 MHz sysclk = 8 MHz sysclk = 16 MHz TFIRCSU CC C Fast internal RC oscillator start-up time -- -- -- TA = 55 C VDD = 5.0 V 10% VDD = 3.3 V 10% TA = 125 C VDD = 5.0 V 10% VDD = 3.3 V 10% TA = 25 C FIRCPRE CC C Fast internal RC oscillator precision after software trimming of fFIRC FIRCTRIM CC C Fast internal RC oscillator trimming step FIRCVAR CC C Fast internal RC oscillator variation over temperature and supply with respect to fFIRC at TA = 25 C in high-frequency configuration TA = 25 C -- -- -5 1.6 -- +5 % % VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified. All values need to be confirmed during device validation. 3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 1 2 3.16 Slow internal RC oscillator (128 kHz) electrical characteristics Table 36. Slow internal RC oscillator (128 kHz) electrical characteristics Symbol fSIRC ISIRC3, C Parameter Conditions1 Min CC P Slow internal RC oscillator low frequency SR -- CC C Slow internal RC oscillator low frequency current TA = 25 C, trimmed -- TA = 25 C, trimmed -- 100 -- Value2 Unit Typ 128 -- -- Max -- 150 5 A kHz The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock for the RTC module. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 49 Electrical characteristics Table 36. Slow internal RC oscillator (128 kHz) electrical characteristics (continued) Symbol TSIRCSU SIRCPRE SIRCTRIM SIRCVAR C Parameter Conditions 1 Value2 Unit -- -2 8 -- 2.7 -- 12 +2 -- +10 % s % Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Min Typ Max CC P Slow internal RC oscillator start-up TA = 25 C, VDD = 5.0 V 10% time CC C Slow internal RC oscillator precision TA = 25 C after software trimming of fSIRC CC C Slow internal RC oscillator trimming step -- -- -10 CC C Slow internal RC oscillator variation High frequency configuration in temperature and supply with respect to fSIRC at TA = 55 C in high frequency configuration VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified. All values need to be confirmed during device validation. 3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 1 2 3.17 3.17.1 ADC electrical characteristics Introduction The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit and 12-bit). MPC5607B Microcontroller Data Sheet, Rev. 3 50 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Offset Error OSE 1023 Gain Error GE 1022 1021 1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2) code out 7 (1) 6 5 (5) 4 (4) 3 (3) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal) Offset Error OSE Figure 15. ADC0 characteristic and error definitions 3.17.2 Input impedance and ADC accuracy In the following analysis, the input circuit corresponding to the precise channels is considered. To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 51 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrical characteristics Eqn. 4 R S + R F + R L + R SW + R AD -1 V A * -------------------------------------------------------------------------- < -- LSB R EQ 2 Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1 Sampling Source RS Filter RF Current Limiter RL RAD VA CF CP1 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 16. Input equivalent circuit (precise channels) MPC5607B Microcontroller Data Sheet, Rev. 3 52 Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 4: Electrical characteristics EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1 Extended Switch RSW2 Sampling Source RS Filter RF Current Limiter RL RAD VA CF CP1 CP3 CP2 CS RS RF CF RL RSW RAD CP CS Source Impedance Filter Resistance Filter Capacitance Current Limiter Resistance Channel Selection Switch Impedance (two contributions RSW1 and RSW2) Sampling Switch Impedance Pin Capacitance (three contributions, CP1, CP2 and CP3) Sampling Capacitance Figure 17. Input equivalent circuit (extended channels) A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 16): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). VCS VA VA2 Voltage Transient on CS V < 0.5 LSB 1 2 1 < (RSW + RAD) CS << TS VA1 2 = RL (CS + CP1 + CP2) TS t Figure 18. Transient behavior during sampling phase In particular two different transient periods can be distinguished: 1. A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 53 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrical characteristics CP * CS 1 = ( R SW + R AD ) * -------------------CP + CS Eqn. 5 Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant: Eqn. 6 1 < ( R SW + R AD ) * C S T S The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 7: Eqn. 7 V A1 * ( C S + C P1 + C P2 ) = V A * ( C P1 + C P2 ) 2. A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: Eqn. 8 2 < R L * ( C S + C P1 + C P2 ) In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained: Eqn. 9 10 * 2 = 10 * R L * ( C S + C P1 + C P2 ) < TS Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge balance assuming now CS already charged at VA1): Eqn. 10 VA2 * ( C S + C P1 + C P2 + C F ) = V A * C F + V A1 * ( C P1 + C P2 + C S ) The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing. MPC5607B Microcontroller Data Sheet, Rev. 3 54 Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrical characteristics Analog source bandwidth (VA) Noise TC < 2 RFCF (Conversion rate vs. filter pole) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages fF = f0 (Anti-aliasing filtering condition) 2 f0 < fC (Nyquist) f0 f Sampled signal spectrum (fC = Conversion rate) Anti-aliasing filter (fF = RC filter pole) fF f f0 fC f Figure 19. Spectral representation of input signal Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS: Eqn. 11 VA C P1 + C P2 + C F ----------- = ------------------------------------------------------V A2 C P1 + C P2 + C F + C S From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: ADC0 (10-bit) C F > 2048 * C S ADC1 (12-bit) C F > 8192 * C S Eqn. 13 Eqn. 12 MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 55 Electrical characteristics 3.17.3 ADC electrical characteristics Table 37. ADC input leakage current Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Value Symbol C Parameter Conditions Min Typ 1 1 8 45 Max -- -- 200 400 -- -- -- -- Unit nA ILKG CC C Input leakage current TA = -40 C No current injection on adjacent pin C C P TA = 25 C TA = 105 C TA = 125 C Table 38. ADC conversion characteristics (10-bit ADC0) Symbol VSS_ADC0 SR C -- Paramete r Voltage on VSS_HV_ ADC0 (ADC0 reference) pin with respect to ground (VSS)2 Voltage on VDD_HV_ ADC pin (ADC reference) with respect to ground (VSS) Analog input voltage3 ADC0 analog frequency Conditions1 Min -- -0.1 Value Unit Typ -- Max 0.1 V VDD_ADC0 SR -- -- VDD-0.1 -- VDD+0.1 V VAINx SR -- -- VSS_ADC0 -0.1 6 -- VDD_ADC0 +0.1 32 + 4% V fADC0 SR -- -- -- MHz ADC0_SY S SR -- ADC0 ADCLKSEL = 14 digital clock duty cycle (ipg_clk) ADC0 power up delay -- 45 -- 55 % tADC0_PU SR -- -- -- 1.5 s MPC5607B Microcontroller Data Sheet, Rev. 3 56 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 38. ADC conversion characteristics (continued)(10-bit ADC0) Symbol tADC0_S CC C T Paramete r Sample time5 Conditions1 Min fADC = 32 MHz, ADC0_conf_sample_i nput = 17 fADC = 6 MHz, INPSAMP = 255 tADC0_C CS CC CC P D Conversio fADC = 32 MHz, n time6 ADC_conf_comp = 2 ADC0 input sampling capacitan ce ADC0 input pin capacitan ce 1 ADC0 input pin capacitan ce 2 ADC0 input pin capacitan ce 3 Internal resistance of analog source Internal resistance of analog source Internal resistance of analog source Input current Injection Current injection on one ADC0 input, different from the converted one -- 0.625 -- 0.5 Value Unit -- s Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 57 Preliminary--Subject to Change Without Notice Typ Max -- -- -- 42 s 3 pF CP1 CC D -- -- -- 3 pF CP2 CC D -- -- -- 1 pF CP3 CC D -- -- -- 1 pF RSW1 CC D -- -- -- 3 k RSW2 CC D -- -- -- 2 k RAD CC D -- -- -- 2 k IINJ SR -- VDD = 3.3 V 10% VDD = 5.0 V 10% -5 -- 5 mA -5 -- 5 MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics Table 38. ADC conversion characteristics (continued)(10-bit ADC0) Symbol | INL | CC C T Paramete r Conditions1 Min -- Value Unit 0.5 1.5 LSB Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Typ Max Absolute No overload value for integral non-linear ity Absolute No overload differential non-linear ity Absolute offset error Absolute gain error -- | DNL | CC T -- 0.5 1.0 LSB | OFS | CC T -- 0.5 -- LSB | GNE | TUEP CC CC T P T -- -- -2 -3 0.6 0.6 -- 2 3 LSB LSB Total Without current unadjuste injection d error7 for With current injection precise channels, input only pins Total Without current unadjuste injection d error7 for With current injection extended channel TUEX CC T T -3 -4 1 3 4 LSB 1 2 3 4 5 6 7 VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified. Analog and digital VSS must be common (to be tied together externally). VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal divider by 2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the end of the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC0_S depend on programming. This parameter does not include the sample time tADC0_S, but only the time for determining the digital result and the time to load the result's register with the conversion result. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors. MPC5607B Microcontroller Data Sheet, Rev. 3 58 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Offset Error OSE 4095 Gain Error GE 4094 4093 4092 4091 1 LSB ideal = AVDD / 4096 4090 (2) code out 7 (1) 6 5 (5) 4 (4) 3 (3) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 Vin(A) (LSBideal) Offset Error OSE Figure 20. ADC1 characteristic and error definitions MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 59 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrical characteristics Table 39. Conversion characteristics (12-bit ADC1) Symbol VSS_ADC1 SR Parameter Voltage on VSS_HV_A DC1 (ADC1 reference) pin with respect to ground (VSS)2 Voltage on VDD_HV_ ADC1 pin (ADC1 reference) with respect to ground (VSS) Analog input voltage3 ADC1 analog frequency ADC1 power up delay Conditions1 Min -- -0.1 Value Unit 0.1 V Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Typ Max VDD_ADC1 SR -- VDD-0.1 VDD+0.1 V VAINx SR -- VSS_ADC1-0 .1 32 + 3% VDD_ADC1+ 0.1 32 + 4% V fADC1 SR -- MHz tADC1_PU SR -- 1.5 s tADC1_S CC fADC1= 32 MHz, Sample time4 ADC1_conf_sample_inp VDD=3.3 V ut = 20 Sample time4 VDD =5.0 V Sample time4 VDD=3.3 V fADC1= 32 MHz, ADC1_conf_sample_inp ut = 17 fADC1= 3.33 MHz, ADC1_conf_sample_inp ut = 255 600 ns 500 76.2 s fADC1= 3.33 MHz, Sample time4 ADC1_conf_sample_inp VDD =5.0 V ut = 255 76.2 MPC5607B Microcontroller Data Sheet, Rev. 3 60 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 39. Conversion characteristics (12-bit ADC1) (continued) Symbol tADC1_C CC Parameter Conditions1 Min Conversion fADC1 = 20MHz, time5 ADC1_conf_comp = 0 VDD=3.3 V Conversion fADC 1= 13.33 MHz, time5 ADC1_conf_comp = 0 VDD =5.0 V Conversion fADC 1= 13.33 MHz, time5 ADC1_conf_comp = 0 VDD=3.3 V Conversion fADC1 = 32 MHz, time5 ADC1_conf_comp = 0 VDD =5.0 V ADC0_SYS SR ADC1 ADCLKSEL = 16 digital clock duty cycle (ipg_clk) ADC1 input sampling capacitanc e ADC1 input pin capacitanc e1 ADC1 input pin capacitanc e2 ADC1 input pin capacitanc e3 Internal resistance of analog source Internal resistance of analog source Internal resistance of analog source -- 45 2.4 Value Unit s Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 61 Preliminary--Subject to Change Without Notice Typ Max 1.5 s 3.6 s 3.6 s -- 55 % CS CC 5 pF CP1 CC -- 3 pF CP2 CC -- 1 pF CP3 CC -- 1.5 pF RSW1 CC -- 1 k RSW2 CC -- 2 k RAD CC -- 0.3 k MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics Table 39. Conversion characteristics (12-bit ADC1) (continued) Symbol IINJ SR Parameter Input current Injection Conditions1 Min Current injection on one ADC1 input, different from the converted one VDD = 3.3 V 10% VDD = 5.0 V 10% -5 -5 Value Unit -- -- 5 5 mA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Typ Max INLP CC Absolute No overload Integral non-linearit y-Precise channels Absolute No overload Integral non-linearit y-Extended channels Absolute No overload Differential non-linearit y Absolute Offset error Absolute Gain error -- -- 1 3 LSB INLX CC 1.5 5 LSB DNL CC 0.5 1 LSB OFS GNE TUEP7 CC CC CC 2 2 LSB LSB Total Unadjusted Without current injection Error for precise With current injection channels, input only pins Total Unadjusted Without current injection Error for extended With current injection channel -6 -8 6 8 TUEX7 CC -10 -12 10 12 LSB LSB 1 2 VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 / 125 C, unless otherwise specified. Analog and digital VSS must be common (to be tied together externally). 3V AINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0xFFF. 4 During the sample time the input capacitance C can be charged/discharged by the external source. The internal S resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end of the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC1_S depend on programming. MPC5607B Microcontroller Data Sheet, Rev. 3 62 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 5 MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 63 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages This parameter does not include the sample time tADC1_S, but only the time for determining the digital result and the time to load the result's register with the conversion result. 6 Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal divider by 2. 7 Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors. Electrical characteristics 3.18 3.18.1 On-chip peripherals Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Current consumption Table 40. On-chip peripherals current consumption1 Value Symbol C CC T Parameter Conditions Min Typ Max A Total (static + dynamic) consumpti on: * FlexCAN in loop-ba ck mode * XTAL@8 MHz used as CAN engine clock source * Message sending period is 580 s 7.652 * fperiph + 84.73 8.0743 * fperiph + 26.757 Unit IDD_BV(CAN ) 500 Kbps CAN (FlexCAN) 125 Kbps supply current on VDD_BV IDD_BV(eMI OS) CC T eMIOS Static consumption: supply * eMIOS channel OFF current on * Global prescaler VDD_BV enabled Dynamic consumption: * It does not change varying the frequency (0.003 mA) 28.7 * fperiph 3 IDD_BV(SCI) CC T SCI Total (static + dynamic) (LINFlex) consumption: supply * LIN mode current on * Baudrate: 20 Kbps VDD_BV SPI (DSPI) Ballast static consumption (only supply current on clocked) VDD_BV Ballast dynamic consumption (continuus communication): * Baudrate: 2 Mbit * Trasmission every 8 s * Frame: 16 bits 4.7804 * fperiph + 30.946 IDD_BV(SPI) CC T 1 16.3 * fperiph MPC5607B Microcontroller Data Sheet, Rev. 3 64 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 40. On-chip peripherals current consumption1 (continued) Value Symbol IDD_BV(ADC ) C CC T Parameter ADC supply current on VDD_BV Conditions Min VDD = 5.5 V Ballast static consumpti on (no conversion ) Ballast dynamic consumpti on (continuus conversion ) Typ 0.0409 * fperiph Max Unit mA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 65 VDD = 5.5 V 0.0049 * fperiph IDD_HV_AD C(ADC) CC T VDD = 5.5 ADC Analog supply V static consumpti current on on (no VDD_HV_AD conversion C ) VDD = 5.5 V Analog dynamic consumpti on (continuus conversion ) - 0.0017 * fperiph 0.075 * fperiph + 0.032 IDD_HV(FLA SH) CC T CFlash + VDD = 5.5 DFlash V supply current on VDD_HV_AD C 13.25 IDD_HV(PLL) CC T PLL supply VDD = 5.5 current on V VDD_HV - 0.0031 * fperiph 1 Operating conditions: TA = 25 C, fperiph = 8 MHz to 64 MHz MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice Electrical characteristics 3.18.2 DSPI characteristics Table 41. DSPI characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Value No. 1 -- -- Symbol tSCK fDSPI tCSC SR SR CC C D D D Parameter Min SCK cycle time DSPI digital controller frequency Internal delay between pad associated to SCK and pad associated to CSn in master mode CS to Master SCK delay mode Slave mode After SCK Master delay mode Slave mode SCK duty Master cycle mode Slave mode Slave access time Slave SOUT disable time -- 64 -- -- Typ -- -- -- Max -- fCPU 1201 Unit ns MHz ns 2 tCSCext2 CC SR D D D D D D D tCSCext = tCSC + tCSC 32 -- -- ns 3 tASCext3 CC SR tASCext = tASC + tCSC 1/fDSPI + 5 ns -- tSCK/2 27 -- tSCK/2 -- -- -- -- -- -- ns ns ns 4 tSDC CC SR 5 tA SR ns 6 tDI SR D -- 0 -- -- ns 7 tSUI SR D Data Master setup time (MTFE = for inputs 0) Slave Master (MTFE = 1) 35 -- -- ns 5 35 -- -- -- -- 8 tHI SR D Data hold Master time for (MTFE = inputs 0) Slave Master (MTFE = 1) 0 -- -- ns 24 0 -- -- -- -- MPC5607B Microcontroller Data Sheet, Rev. 3 66 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 41. DSPI characteristics (continued) Value No. 9 Symbol tSUO5 CC C D Parameter Min Data valid Master after SCK (MTFE = edge 0) Slave Master (MTFE = 1) 10 tHO5 CC D Data hold Master time for (MTFE = outputs 0) Slave Master (MTFE = 1) 1 2 Unit -- -- 32 ns Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 67 Typ Max -- -- -- -- 34 32 2 -- -- ns 5.5 2 -- -- -- -- Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad. The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tCSC to ensure positive tCSCext. 3 The t ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tASC to ensure positive tASCext. 4 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register. 5 SCK and SOUT configured as MEDIUM pad MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice Electrical characteristics Figure 21. DSPI classic SPI timing - master, CPHA = 0 2 PCSx 4 SCK Output (CPOL = 0) 4 1 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale Semiconductor SCK Output (CPOL = 1) 10 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data Note: Numbers shown reference Table 41. Figure 22. DSPI classic SPI timing - master, CPHA = 1 PCSx SCK Output (CPOL = 0) 10 SCK Output (CPOL = 1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data Note: Numbers shown reference Table 41. MPC5607B Microcontroller Data Sheet, Rev. 3 68 Preliminary--Subject to Change Without Notice Electrical characteristics Figure 23. DSPI classic SPI timing - slave, CPHA = 0 SS 1 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN 10 Data Last Data 12 Data 11 Last Data 6 4 First Data Note: Numbers shown reference Table 41. Figure 24. DSPI classic SPI timing - slave, CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 5 SOUT 11 12 First Data 9 10 Data Last Data Data Last Data 6 SIN First Data Note: Numbers shown reference Table 41. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 69 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 2 3 Electrical characteristics Figure 25. DSPI modified transfer format timing - master, CPHA = 0 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages PCSx 4 2 SCK Output (CPOL = 0) SCK Output (CPOL = 1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1 10 Note: Numbers shown reference Table 41. Figure 26. DSPI modified transfer format timing - master, CPHA = 1 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) 9 SIN First Data Data 12 SOUT First Data Data 10 Last Data 11 Last Data Note: Numbers shown reference Table 41. MPC5607B Microcontroller Data Sheet, Rev. 3 70 Preliminary--Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Figure 27. DSPI modified transfer format timing - slave, CPHA = 0 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 71 Preliminary--Subject to Change Without Notice 2 SS 1 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 4 6 Last Data 10 Last Data Note: Numbers shown reference Table 41. Figure 28. DSPI modified transfer format timing - slave, CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 5 SOUT 11 12 First Data 9 10 Data Last Data Data Last Data 6 SIN First Data Note: Numbers shown reference Table 41. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics 72 PCSS PCSx 7 8 Figure 29. DSPI PCS strobe (PCSS) timing MPC5607B Microcontroller Data Sheet, Rev. 3 Preliminary--Subject to Change Without Notice Note: Numbers shown reference Table 41. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Electrical characteristics 3.18.3 Nexus characteristics Table 42. Nexus characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 73 Preliminary--Subject to Change Without Notice Value No. 1 2 3 4 5 6 Symbol tTCYC tMCYC tMDOV tMSEOV tEVTOV tNTDIS tNTMSS C Parameter Min Typ -- -- -- -- -- -- -- -- -- -- -- Max -- -- 8 8 8 -- -- -- -- -- -- 64 32 -- -- -- 15 15 5 5 35 6 Unit ns ns ns ns ns ns ns ns ns ns ns CC D TCK cycle time CC D MCKO cycle time CC D MCKO low to MDO data valid CC D MCKO low to MSEO_b data valid CC D MCKO low to EVTO data valid CC D TDI data setup time CC D TMS data setup time CC D TDI data hold time CC D TMS data hold time CC D TCK low to TDO data valid CC D TCK low to TDO data invalid 7 tNTDIH tNTMSH 8 9 tTDOV tTDOI Figure 30. Nexus TDI, TMS, TDO timing TCK 10 11 TMS, TDI 12 TDO Note: Numbers shown reference Table 42. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Electrical characteristics 3.18.4 JTAG characteristics Table 43. JTAG characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Value No. 1 2 3 4 5 6 7 Symbol tJCYC tTDIS tTDIH tTMSS tTMSH tTDOV tTDOI CC CC CC CC CC CC CC C Parameter Min Typ -- -- -- -- -- -- 6 -- Max -- -- -- -- -- 33 -- 64 15 5 15 5 Unit ns ns ns ns ns ns ns D TCK cycle time D TDI setup time D TDI hold time D TMS setup time D TMS hold time D TCK low to TDO valid D TCK low to TDO invalid Figure 31. Timing diagram - JTAG boundary scan TCK 2/4 3/5 DATA INPUTS 6 INPUT DATA VALID DATA OUTPUTS OUTPUT DATA VALID 7 DATA OUTPUTS Note: Numbers shown reference Table 43. MPC5607B Microcontroller Data Sheet, Rev. 3 74 Preliminary--Subject to Change Without Notice Freescale Semiconductor 4 4.1 4.1.1 Freescale Semiconductor Package characteristics Package mechanical data 176 LQFP MPC5607B Microcontroller Data Sheet, Rev. 3 Figure 32. 176 LQFP package mechanical drawing (Part 1 of 3) Preliminary--Subject to Change Without Notice Package characteristics 75 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Package characteristics 76 MPC5607B Microcontroller Data Sheet, Rev. 3 Figure 33. 176 LQFP package mechanical drawing (Part 2 of 3) Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale Semiconductor MPC5607B Microcontroller Data Sheet, Rev. 3 Figure 34. 176 LQFP package mechanical drawing (Part 3 of 3) Preliminary--Subject to Change Without Notice Package characteristics 77 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Package characteristics Table 44. LQFP176 mechanical data1 mm Symbol A A1 A2 b C D E e HD HE L 3 inches2 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Max 1.600 0.150 1.450 0.270 0.200 24.100 24.100 0.002 0.053 0.007 0.004 0.941 0.941 0.020 26.100 26.100 0.750 1.020 1.020 0.018 0.039 0.049 0.049 7 0 inches 0.0031 7 1.028 1.028 0.030 0.057 0.011 0.008 0.949 0.949 Min Typ Max 0.063 Min 1.400 0.050 1.350 0.170 0.090 23.900 23.900 Typ 0.500 25.900 25.900 0.450 1.000 1.250 1.250 0 mm 0.080 L1 ZD ZE q Tolerance ccc 1 2 Controlling dimension: millimeter Values in inches are converted from mm and rounded to 4 decimal digits. 3 L dimension is measured at gauge plane at 0.25 mm above the seating plane MPC5607B Microcontroller Data Sheet, Rev. 3 78 Preliminary--Subject to Change Without Notice Freescale Semiconductor 4.1.2 Freescale Semiconductor 144 LQFP MPC5607B Microcontroller Data Sheet, Rev. 3 Figure 35. 144 LQFP package mechanical drawing (Part 1 of 2) Preliminary--Subject to Change Without Notice Package characteristics 79 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Package characteristics 80 MPC5607B Microcontroller Data Sheet, Rev. 3 Figure 36. 144 LQFP package mechanical drawing (Part 2 of 2) Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Package characteristics Table 45. LQFP144 mechanical data mm Symbol Min A A1 A2 b c D D1 D3 E E1 E3 e L L1 k Tolerance ccc 1 inches1 Max 1.600 Min Typ Max 0.0630 0.0020 0.0531 0.0067 0.0035 0.8583 0.7795 0.8661 0.7874 0.6890 22.200 20.200 0.8583 0.7795 0.8661 0.7874 0.6890 0.0197 0.750 0.0177 0.0236 0.0394 7.0 3.5 0.0 inches 0.0031 7.0 0.0295 0.8740 0.7953 0.0551 0.0087 0.0059 0.0571 0.0106 0.0079 0.8740 0.7953 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 81 Typ 0.050 1.350 0.170 0.090 21.800 19.800 22.000 20.000 17.500 21.800 19.800 22.000 20.000 17.500 0.500 0.450 0.600 1.000 0.0 3.5 mm 0.080 1.400 0.220 0.150 1.450 0.270 0.200 22.200 20.200 Values in inches are converted from mm and rounded to 4 decimal digits. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice Package characteristics 82 4.1.3 100 LQFP MPC5607B Microcontroller Data Sheet, Rev. 3 Figure 37. 100 LQFP package mechanical drawing (Part 1 of 3) Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale Semiconductor Package characteristics MPC5607B Microcontroller Data Sheet, Rev. 3 Figure 38. 100 LQFP package mechanical drawing (Part 2 of 3) Preliminary--Subject to Change Without Notice 83 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Package characteristics 84 MPC5607B Microcontroller Data Sheet, Rev. 3 Figure 39. 100 LQFP package mechanical drawing (Part 3 of 3) Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Package characteristics Table 46. LQFP100 mechanical data mm Symbol A A1 A2 b c D D1 D3 E E1 E3 e L L1 k Tolerance ccc 1 inches1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 85 Max 1.600 Min Typ Max 0.0630 0.0020 0.0531 0.0067 0.0035 0.6220 0.5433 0.6299 0.5512 0.4724 16.200 14.200 0.6220 0.5433 0.6299 0.5512 0.4724 0.0197 0.750 0.0177 0.0236 0.0394 7.0 0.0 3.5 inches 0.0031 7.0 0.0295 0.6378 0.5591 0.0551 0.0087 0.0059 0.0571 0.0106 0.0079 0.6378 0.5591 Min Typ 0.050 1.350 0.170 0.090 15.800 13.800 16.000 14.000 12.000 15.800 13.800 16.000 14.000 12.000 0.500 0.450 0.600 1.000 0.0 3.5 mm 0.080 1.400 0.220 0.150 1.450 0.270 0.200 16.200 14.200 Values in inches are converted from mm and rounded to 4 decimal digits. MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice Package characteristics 86 4.1.4 208MAPBGA MPC5607B Microcontroller Data Sheet, Rev. 3 Figure 40. 208 MAPBGA package mechanical drawing (Part 1 of 2) Preliminary--Subject to Change Without Notice Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Package characteristics Figure 41. 208 MAPBGA package mechanical drawing (Part 2 of 2) Table 47. LBGA208 mechanical data mm Symbol Min A A1 A2 A3 A4 b 0.50 0.60 0.30 1.085 0.30 0.80 0.70 0.0197 0.0236 Typ Max 1.70 0.0118 0.0427 0.0118 0.0315 0.0276 3 inches1 Notes Min Typ Max 0.0669 2 MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 87 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Package characteristics Table 47. LBGA208 mechanical data (continued) mm Symbol Min D D1 E E1 e F ddd eee fff 1 2 inches1 Notes Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Max 17.20 Min 0.6614 Typ 0.6693 0.5906 17.20 0.6614 0.6693 0.5906 0.0394 0.0394 0.20 0.25 0.10 0.0079 0.0098 0.0039 4 5 Typ 17.00 15.00 Max 0.6772 16.80 16.80 17.00 15.00 1.00 1.00 0.6772 Values in inches are converted from mm and rounded to 4 decimal digits. LBGA stands for Low profile Ball Grid Array. - Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the component - The maximum total package height is calculated by the following methodology: A2 Typ+A1 Typ + (A12+A32+A42 tolerance values) - Low profile: 1.20mm < A < 1.70mm 3 The typical ball diameter before mounting is 0.60mm. 4 The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 5 The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones. MPC5607B Microcontroller Data Sheet, Rev. 3 88 Preliminary--Subject to Change Without Notice Freescale Semiconductor Ordering information 5 Ordering information Figure 42. Commercial product code structure Example code: Qualification Status PowerPC Core Automotive Platform Core Version Flash Size (core dependent) Product Optional fields Temperature spec. Package Code R = Tape & Reel (blank if Tray) M PC 56 0 7 B E M LL R Qualification Status M = MC status S = Auto qualified P = PC status Flash Size (z0 core) 5 = 768 KB 6 = 1024 KB 7 = 1.5 MB Temperature spec. C = -40 C to 85C V = -40 C to 105C M = -40 C to 125C Automotive Platform 56 = PPC in 90nm 57 = PPC in 65nm Product B = Body C = Gateway Package Code LL = 100 LQFP LQ = 144 LQFP LU= 176 LQFP 1 208 MAPBGA available only as development package for Nexus2+ MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 89 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Revision history 6 Revision history Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Table 48 summarizes revisions to this document. Table 48. Revision history Revision 1 2 Date 12-Jan-2009 Initial release 09 Nov-2009 Updated Features -Replaced 27 IRQs in place of 23 -ADC features -External Ballast resistor support conditions -updated device summary-added 208 BGA details -updated block diagram to include WKUP -updated block diagram to include 5 ch ADC 12 -bit -updated Block summary table -updated LQFP 144, 176 and 100 pinouts. Applied new naming convention for ADC signals as ADCx_P[x] and ADCx_S[x] Section 1, "General description -updated Bolero 1.5M device comparison table -updated block diagram-aligned with 512k -updated block summary-aligned with 512k Section 2, "Package pinouts -updated 100,144,176,208 packages according to cut2.0 changes Added Section 3.5.1, "External ballast resistor recommendations Added NVUSRO [WATCHDOG_EN] field description updated Absolute maximum ratings updated LQFP thermal characteristics updated I/O supply segments updated Voltage regulator capacitance connection updated Low voltage monitor electrical characteristics updated Low voltage power domain electrical characteristics updated DC electrical characteristics updated Program/Erase specifications updated Conversion characteristics (10 bit ADC) updated FMPLL electrical characteristics updated Fast RC oscillator electrical characteristics-aligned with Bolero 512K updated On-chip peripherals current consumption updated ADC characteristics and error definitions diagram updated ADC conversion characteristics (10 bit and 12 bit) Added ADC characteristics and error definitions diagram for 12 bit ADC 25 Jan-2010 Updated Features Updated block diagram to connect peripherals to pad I/O Updated block summary to include ADC 12-bit Updated 144, 176 and 100 pinouts to adjust format issues Table 26 Flash module life-retention value changed from 1-5 to 5 yrs Minor editing changes Substantive changes 3 MPC5607B Microcontroller Data Sheet, Rev. 3 90 Preliminary--Subject to Change Without Notice Freescale Semiconductor Abbreviations Appendix A Abbreviations Table 49 lists abbreviations used but not defined elsewhere in this document. Table 49. Abbreviations Abbreviation CMOS CPHA CPOL CS EVTO LED MCKO MDO MSEO MTFE SCK SOUT TBD TCK TDI TDO TMS Meaning Complementary metal-oxide-semiconductor Clock phase Clock polarity Peripheral chip select Event out Light emitting diode Message clock out Message data out Message start/end out Modified timing format enable Serial communications clock Serial data out To be defined Test clock input Test data input Test data output Test mode select Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages 91 Preliminary--Subject to Change Without Notice MPC5607B Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com Freescale Semiconductor Literature Distribution Center 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2009. All rights reserved. MPC5607B Rev. 3 01/2010 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages |
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